Job Details:
Job Description:
- As part of the front end team, you will be critical to the future success of Intel's SoC products by enabling tomorrow today.
- Intel's Front-End CAD is a research and development team that develops and delivers Solutions (TFMs: Tools, Flows, Methods) for complete front end system including static lint checking, functional and formal verification, emulation, front end signoff, IP and SOC Quality checking and methodology that are critical to enabling SW/HW co-design and accelerate time to market for our SoCs.
- As part of this team, you will be developing and applying computer aided design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems in RTL solutions space
- Assessing architecture and hardware limitations, plans technical projects in the design and development of CAD software.
- Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters that will aid better PPA, quality and runtime
- FECAD is a highly exciting and challenging environment. We are exposed to broad scope of mission critical SoC challenges and are looking for qualified engineers with several soft skills including:
- Having hands on exposure to Front End RTL solution space, with an understanding of the challenges and problems in this space
- Capability to explore, evaluate and derive new improved methodologies in the FE design implementation for IPs/SoCs/Subsystems, and integrate them in the existing design systems for use by design team
- Ability to act as ambassador for new technologies and actively engage with global cross-site teams
- Ability to lead projects, delegate tasks and motivate engineers
- Excellent communication and presentation skills
- Ability to work independently, prioritize, manage risks, evaluate tradeoffs, make quick decisions and communicate project status
- Interfacing with multiple customers, understanding their requirements, setting expectations and delivering on commitments.
- Ability to work with hardware and software teams developing advanced technologies using design and SW best practices
- Analytical problem solving, team oriented and ability to work in a collaborative environment
Qualifications:
- BS/BTech or MS/PhD degree in Electrical Engineering, or Computer Engineering or related disciplines.
- BS/BTech with 10 years of experience or MS/MTech/PhD with 8 years of relevant industry experience.
Minimum Requirements:
- Front End domain tools, flows and methodologies and its applications with AI- Static Checks, Synthesis, Signoff Checks, Formal and Functional Verification, Integration Handoff, Design and RTL ( IP/SOC) Quality checks, Simulation
- Experience with Python, Shell scripting, Makefiles, Dart
- Knowledge and experience of logic/RTL design using Verilog, System Verilog
- Knowledge of Linux/Unix and testing environments and tools.
- Ability to communicate effectively with various technical groups and design customers and to coordinate activities amongst those groups
- Team Player
Job Type:
Experienced HireShift:
Shift 1 (India)Primary Location:
India, BangaloreAdditional Locations:
Business group:
Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust
N/AWork Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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