Job Details:

Job Description: 

Fab Sort Manufacturing (FSM) is responsible for the production of all Intel silicon using some of the world's most advanced manufacturing processes in fabs in Arizona, Ireland, Israel, Oregon and 2 new greenfield sites in Ohio and Germany. As part of Intel's strategy, FSM is rapidly expanding its operation to deliver output for both internal and foundry customers with state-of-the-art technologies arriving in High-Volume Manufacturing (HVM) at a 2-year cadence going forward.
Intel recently created the HVM Global Yield organization in FSM to strengthen its yield operation and enable fast-paced yield ramp-up in early HVM phases for each technology in collaboration with Technology Development team and FSM fab managers.

This position is for a Senior Engineer in the Device Integration team in the FSM HVM Global Yield organization, reporting to the Manager/Director of Device Integration Engineering. The selected candidate will work with other members in Global Yield org including Process Integration, Yield Analysis and Defect engineering teams, fab module/yield teams and TD team members to achieve yield ramp-up and process optimization in early production stage, supporting internal and external customers.

The Device Integration engineer's responsibilities include (but are not limited to):

• Own engineering projects to execute HVM yield roadmap, device targeting and attain performance targets.
• Collaborate with Technology Development team to develop new device technology, customize device architecture per customer request and import to production fabs.
• Participate or lead cross-organizational team of engineers to identify root cause of device-related yield/performance issues and define mitigation plan to meet committed production yield/performance targets.
• Own NPI (New Product Introduction) in production fabs and perform device-related process optimization to meet foundry customers product specifications and requirements.
• Develop a model to predict device performance accurately in early-to-mid stage of Si progression and drive systematic solution to maintain baseline device performance.
• Work with Process Integration engineers to drive process simplification and implement cost reduction engineering opportunities in line.

#foundry

Important:  Please be informed that Intel is proactively trying to find candidates for a foundry engineering position which is frequently available at Intel US.  Please note that the position may not be available at this time.  If you would be interested in this position should it become available, we would encourage you to apply, and our hiring team will be glad to contact you when/if relevant. 

Qualifications:

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Physics or Materials Science major. Other related science and engineering degrees can be considered based on industry experience.
• 6+ years' experience in advanced node semiconductor industry in Device Integration.
• Experience in FinFET technology development or high-volume manufacturing.
• Experience with Device Physics and hands-on application in real-world fab environment.
• Experience with FEOL (Front-End-Of-Line) Integration teams including Fin, Poly, Source-Drain and Gate segments on Device performance improvement and targeting with technical understanding on how FEOL process changes impact Device parameters.

Preferred Qualifications:

• Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics or Materials Science major.
• Experience in project/program management and/or Task Force Team lead.
• Demonstrated interpersonal skills including influencing, engaging, and motivating.
• Experience in serving external Foundry customers through technical interactions.
• Experience in GAA (Gate-All-Around) technology architecture.
• Experience in new semiconductor technology development.
• Basic understanding and collaboration experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.

          

Job Type:

Shift:

Shift 1 (Taiwan)

Primary Location: 

Taiwan, Hsinchu

Additional Locations:

Business group:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.