External Technology Integration Engineer

Location: US, Arizona, Phoenix

Time Type: Full time

Job Description

Job Details:

Job Description: 

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.

Life at Intel

This role requires regular onsite presence to fulfill essential job responsibilities.

The External Technology Integration Engineer at Intel:

• Leads technical integration of external memory and/or foundry silicon technologies into Intel's advanced packaging platforms
• Drives comprehensive chip-to-package interaction (CPI) assessments across Si backend fab, bump, singulation, assembly, and test domains
• Qualifies breakthrough foundry Si/memory technologies and establish innovative Si far back-end and bump design rules
• Orchestrates complex technical programs with multi-disciplinary stakeholders to deliver game-changing results
• Defines package performance specifications and achieve technology certification through strategic test vehicle design layout and data collections
• Performs feasibility studies and provides integrated process solutions to meet desired safety, quality, reliability and output requirements for ultimate transfer to high volume manufacturing.
• Plans and conducts experiments to fully characterize the process throughout the development cycle and to improve performance for each specific product.
• Identifies integrated process solutions to resolve issues or specific requests from customers by partnering with innovators in product engineering and module engineering teams.
• Leverages big data analysis to identify process design weaknesses and/or manufacturing tool issues and proposes corrective, databased solutions.

A highly qualified candidate will exhibit the following behavior traits:

• Strong platform strategic planning and program management experience.
• Demonstrated written and oral communication skills, particularly to an executive audience.
• Willingness to thrive in ambiguous environments.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Must possess a BA degree in Materials, Chemical Engineering, Chemistry, Physics, Mechanical Engineering with 6+ years of experience in a related field or Master's Degree in Materials, Chemical Engineering, Chemistry, Physics, Mechanical Engineering with 4+ years of experience in a related field or PhD Degree with 2+ years of experience in related field.

Technical experience:
• 3+ years of experience in developing, qualifying to high volume manufacturing of any one or multiple microelectronic packaging processes. Processes include Si far backend fabrication, bump, assembly, substrate or memory manufacturing processes. (or)
• 3+ years of experience in integrating multiple complex semiconductor packaging assembly design, processes, materials and tools towards successful qualification and seamless mass production. (or)
• 3+ years of experience in managing semiconductor technical programs including technical and schedule planning, execution, monitoring and completion of packaging assembly process certifications. (or)
• 3+ years of experience managing semiconductor suppliers processes/materials/tools or managing customers programs against committed schedule.

Preferred Qualifications
• Experience in various versions of 2.5D and 3D advanced package architectures in the industry, their fabrication processes/materials/tools and their interactions.
• Experience in driving yield improvement activities for these advanced package architectures.
• Extensive experience in conducting failure mode and effects analyses (FMEA), technical risk assessments (TRA) and statistical process control (SPC) analyses.
• Experience in defining a silicon - package architecture through fit study, technical risk assessments along with design for yield (DFY) and design for reliability(DFR) considerations.
• Experience in structure property relationships and fundamental materials
characterization techniques
• Experience in model-based problem solving (MBPS) methodologies and quality/yield management through 8D templates
• Familiarity/experience in memory fabrication and packaging processes
• Extensive experience in Si far-backend fab processes, memory/packaging technology, memory silicon/package interactions, silicon and/or package debug and verifications.
• Experience working with foundries, OSATs and familiarity with Si design, tape-in/tape-out processes.
• Experience with silicon design, SI parameters and power characterization and high-speed IO signaling.
• Familiarity/experience with using EDA tools and Si design collaterals.
• Ability to handle and use appropriate (behavioral and/or technical) skills to drive clarity across stakeholders.
• Experience in leading and influencing both internal and external stakeholders towards desired direction and timely execution.
• Excellent verbal and written communication skills.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $155,520.00-298,440.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.