Job Details:

Job Description: 

Drives and develops testability and manufacturability of integrated circuits from the component feasibility stage through the production ramp. Creates, defines and develops system validation environment and test suites. Uses and applies emulation and platform level tools and techniques to ensure performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of failures. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre silicon Validation teams in improving post silicon test content and providing feedback for future on die debug features. Contributes to design, development, and validation of testability circuits, test flows, and methodologies for new products through evaluation, development, and debugging of complex test methods. Interfaces with process development, fab, factory, assembly, quality and reliability, and manufacturing groups to enable post-silicon HVM ramp. Evaluate new designs on automatic test equipment (ATE) and work with the design, DFx, and product development teams to debug functionality and performance issues to root cause. Performs ATE device characterization, utilizes that data to define datasheet specifications, and performs yield analysis. Collaborates with designers to drive design for test/debug/manufacturing (DFT/DFD/DFM) features enabling efficient production testing of new products. Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests validates, modifies, and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability, specifically emphasizing yield analysis and bin split capability. Ensures manufacturability over process and product design through a thorough analysis of process and spec corners and works with design to resolve yield issues before manufacturing ramp. Drives test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations. Analyzes early customer returns with an emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to quality and cost constraints. Leads and drives manufacturing readiness from the fab, assembly, and test factory to support engineering sample and customer sample generation (ES milestones), wafer start planning, product quality execution strategy and capacity analysis, and assembly and test site certification activities. Works with fab, assembly, and test factory partners and planners to support production ramp. May also manage the execution of new product introductions in the fab, fab process targeting, product/process optimizations, and participate in factory task forces to bring product perspective and respond to product issues. Optimizes product supply through data analysis of post-silicon binsplit, die level cherry pick (DLCP), and optimizes sort/test content and yield downstream through data analysis.

Qualifications:

• MS, BS degree in Electrical Engineering or Computer Engineering or equivalent with about 3-7 years of experience.

• Strong in basic electronics, VLSI concepts related CMOS.

• Strong Experience in ATE Test Engineering.

• Experience Testing in Thermal and DTS Module.

• Strong knowledge of Analog, High-speed testing, pad testing architecture, design, methodologies and tools.

• Strong knowledge of DFT architecture, design, methodologies, and tools - DFT, JTAG, etc.

• Some basic knowledge in computer hardware architecture, and basic electronics circuits/logics design knowledge.

• Knowledge on programming languages like Python, C etc will be an advantage.

• Ability to think independently, and process critical thinking behavior.

• Passion to learn, process good problem-solving skills and result orientation.

• A good understanding of Test Engineering and tester debugging is desirable.

• Hands-on design/validation experience with strong/proven debug skills.

• Expertise in Advantest 93K, ATE, and Test Engineering.

• Experience in Teradyne Ultraflex, J750 etc.

A very good team player with good interpersonal, planning, and excellent communication skills.

Requirements listed would be obtained through a combination of industry-relevant job experience, internship experiences, and or schoolwork/classes/research.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.