Senior Electrical System Lead, Workstation

Location: Taipei, Taipei City, Taiwan Region

Time Type: Full time

Job Description

Senior Electrical System Lead, Workstation

Description -

The Senior Electrical System Lead, Workstation serves as the core technical authority accountable for electrical hardware development during the New Product Introduction (NPI) phase—from architecture implementation and schematic lock through Proto, EVT, DVT, and PVT ramp.

In this role, you will lead the technical governance of Original Design Manufacturer (ODM) partners, ensuring that desktop workstation motherboard and electrical subsystems meet stringent performance, reliability, signal/power integrity, schedule milestones, and unit cost/NRE targets before transitioning to sustained production.

Key Responsibilities (NPI Phase Focus)

NPI Architecture & Detailed Design Oversight

• Define and own electrical hardware requirements, platform block diagrams, schematic design guidelines, and PCB stack-up specifications for workstation motherboards and peripheral add-in modules.
• Direct ODM implementation of high-power delivery architectures and cutting-edge high-speed interfaces (PCIe Gen 5/6, DDR5, USB4/Thunderbolt).
• Drive rigorous design review gates (Schematic Review, Layout Pre-Route/Post-Route Review) with ODM engineering teams, ensuring layout conforms to SI simulations, thermal-mechanical constraints, and DFX (DFM/DFT) guidelines prior to tooling/fab release.

ODM Technical Governance & NPI Milestones

• Lead the day-to-day electrical engineering interface with ODM R&D teams (EE, Layout, Power, Thermal, SI, and BIOS/Firmware).
• Govern development execution against predefined phase-gate criteria across all NPI build stages
• Chair weekly technical syncs, action-item tracking, and on-site engineering presence during critical board bring-up milestones and factory trial builds.
• Drive disciplined failure analysis and root cause investigation for functional bugs, power rail instabilities, timing violations, and validation anomalies identified during NPI builds.

Schedule, Cost & Risk Management

• Enforce design schedules with the ODM to ensure board respins, sample deliveries, and validation milestones stay on the critical path.
• Partner with Global Sourcing and Procurement to manage Bill of Materials (BOM) cost and ODM NRE expenditures, driving component selection and qualification of multi-source parts during NPI to avoid post-launch supply chain single points of failure.
• Identify high-risk circuit topologies or component lead-time liabilities, formulating mitigation and contingency layout options.

System Bring-up & Cross-Functional Validation

• Lead joint board bring-up, hardware debugging, and system integration alongside BIOS, Mechanical, Thermal, Power Supply, and Firmware teams.
• Establish manufacturing test coverage requirements (ICT, functional test, boundary scan) and define the technical sign-off criteria.

Required Qualifications

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Experience:
  • 10+ years of experience in complex x86 platform board-level electrical design and system engineering (Intel Xeon/Core, AMD Threadripper/EPYC platforms).
  • 4+ years of direct experience leading ODM/JDM engineering partners through full-cycle NPI execution (Concept through PVT/Ramp).
• Technical Expertise:
  • Demonstrated mastery of high-speed digital interconnects, high-layer-count PCB design rules, and signal/power integrity fundamentals.
  • Deep experience designing and debugging multi-phase VRMs, transient load stepping, power sequencing, and power distribution networks for high-TDP compute hardware.
  • Hands-on laboratory troubleshooting expertise using high-speed oscilloscopes, spectrum analyzers, TDR, logic/protocol analyzers, and thermal imagers.
• Leadership & Execution:
  • Proven capability to hold external development partners strictly accountable to engineering deliverable timelines and milestone budgets.
  • Strong cross-cultural technical communication, leadership, and conflict-resolution skills.

#LI-POST

Job -

Engineering

Schedule -

Full time

Shift -

No shift premium (Taiwan)

Travel -

Relocation -

Equal Opportunity Employer (EEO) - 

HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).

Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.

For more information, review HP’s EEO Policy or read about your rights as an applicant under the law here: “Know Your Rights: Workplace Discrimination is Illegal"