Senior ASIC Design Engineer

Location: Vancouver, Washington, United States of America

Time Type: Full time

Job Description

Senior ASIC Design Engineer

Description -

HP is the world’s leading printing company. We are looking for innovators who are ready to make a purposeful impact. You will be a member of the R&D digital Application-Specific Integrated Circuit (ASIC) design team that develops the main controller with critical HP proprietary intellectual property that separates HP printers from the rest of the competitions. You will work with internal and external partners to deliver industry-leading embedded solutions for future HP printers. 

Our new Vancouver, Washington site expands HP's presence in the Pacific Northwest and serves as a hub for engineering innovation and product development. This location brings together talented engineers working on next-generation technologies that power HP's industry-leading print and imaging solutions. As part of our Imaging & Print organization, you'll help develop advanced imaging capabilities that enhance performance, quality, and customer experiences across HP's enterprise product portfolio.

Responsibilities:

• Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification.

• Proactively work with other team members and partners to align on specifications, drive reviews, and complete documentation.

• Manage and expand relationships with internal and external development partners.

• Be a key contributor to ASIC roadmaps and future innovation.

• Lead cross-discipline task force to triage product HW & FW integration issues to deliver robust solutions.

• Contribute to key areas of Inkjet and Laserjet print architecture and data path requirements.

• Be a key contributor to co-development activities to help prototype ASIC designs in FPGA or other software models to support pre-silicon firmware development and verification.

• Drive design methodology and tool automation work as needed.

Education and Experience Required:

• BS or MS degree in electrical engineering or equivalent with focus on VLSI design experience

• 8 -10 years of ASIC or SOC design and development experience

Knowledge and Skills:

• Deep knowledge of submicron semiconductor technology.

• Deep knowledge of embedded system design, verification, and product development lifecycle.

• Very familiar with digital ASIC/SOC design flow from RTL to silicon characterization

• Very familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.

• Very familiar with design and programming languages: Verilog, SV, Python, Perl, C, C++, etc.

• Very familiar with code base management method including subversion, git, GitHub, etc.

• Excellent analytical and problem-solving skills.

• Excellent written and verbal communication skills, ability to negotiate design features and options

• Working knowledge of electronic components, PCA designs and use of test equipment

Deep knowledge and domain know-hows in one or more areas below is a big plus.

• Laserjet printing technology

• ARM microprocessor subsystem

• Memory and storage subsystem (DDR, Flash, eMMC, etc.)

• Design database management, scripting and other design flow automation

• Proficiency in applying AI Copilot (LLM-based tools) to accelerate ASIC design, verification, and engineering productivity.

The pay range for this role is $116,150 to $182,400 USD annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.

Benefits:

HP offers a comprehensive benefits package for this position, including:

• Health insurance

• Dental insurance

• Vision insurance

• Long term/short term disability insurance

• Employee assistance program

• Flexible spending account

• Life insurance

• Generous time off policies, including;

• 4-12 weeks fully paid parental leave based on tenure

• 11 paid holidays

• Additional flexible paid vacation and sick leave (US benefits overview)

The compensation and benefits information is accurate as of the date of this posting. The Company reserves the right to modify this information at any time, with or without notice, subject to applicable law.

Job -

Engineering

Schedule -

Full time

Shift -

No shift premium (United States of America)

Travel -

No

Relocation -

Yes

Equal Opportunity Employer (EEO) - 

HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).

Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.

For more information, review HP’s EEO Policy or read about your rights as an applicant under the law here: “Know Your Rights: Workplace Discrimination is Illegal"