SoC Design Verification Engineer

Location: Richardson

Time Type: Full time

Job Description

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role

GlobalFoundries is seeking a Staff SoC Design Verification Engineer to verify custom System-on-Chip designs. Working with design and verification engineers across multiple disciplines, the successful candidate will independently own defined verification workstreams, drive closure of verification objectives, solve complex technical problems, improve verification methods, and guide other engineers in the work area.

 

This position is well suited to an experienced verification engineer who has developed broad capability within SoC design verification and is ready to lead portions of projects, solve novel and nonrecurring problems, and drive improvements to existing methods and processes.

Successful candidates are curious, detail-oriented technical leaders who combine hands-on execution, sound engineering judgment, collaborative problem solving, and effective mentoring.

 

Essential Responsibilities

· Review architecture and design specifications to derive verification requirements, risks, and test scenarios.

· Develop and own verification plans for complex blocks, subsystems, or defined portions of larger SoC programs.

· Develop and maintain reusable testbench components, tests, assertions, checkers, scoreboards, and coverage models.

· Drive closure of assigned verification objectives through stimulus development, coverage analysis, and disciplined signoff tracking.

· Independently analyze logs and waveforms and resolve complex, novel, or nonrecurring testbench and design failures.

· Document, communicate, and drive resolution of issues with RTL design, architecture, firmware, and other verification engineers.

· Drive improvements to verification automation, reuse, debug efficiency, and existing development methods.

· Lead technical reviews and train or guide other engineers on verification plans, testbenches, tests, and debug methods.

 

 

Other Responsibilities:

· Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

 

Required Qualifications

· Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 2-4 years of relevant industry experience; OR Bachelor's degree in a related field with 4-5 years of relevant industry experience.

· Demonstrated mastery of multiple aspects of SoC design verification and recognized technical contributions within a work group.

· Advanced experience using SystemVerilog, UVM, constrained-random verification, functional coverage, and SystemVerilog assertions.

· Experience with at least one scripting language, such as Python, Tcl/Tk, Perl, or Shell.

· Experience running EDA verification and debug tools in a UNIX design environment.

· Ability to independently conduct project-based work with limited input on individual tasks.

· Ability to apply specialized knowledge and sophisticated analytical techniques to complex technical problems.

· Ability to improve existing processes and methods and lead development or implementation activities.

· Ability to train, guide, and collaborate with engineers in a technical team.

 

Preferred Qualifications

· Experience with power-aware verification using UPF, including isolation, retention, and power-state transitions.

· Experience with a CPU architecture such as RISC-V, Arm, or MIPS.

· Experience with common SoC protocols or interfaces such as AXI, AHB, APB, SPI, I²C, or UART.

· Experience with UVM RAL, SystemRDL, IP-XACT, or register-model generation flows.

· Experience with formal verification, gate-level simulation, emulation, FPGA prototyping, or hardware/software co-verification.

· C or C++ experience related to embedded software, test development, or reference models.

Expected Salary Range

$106,000.00 - $184,000.00

The exact Salary will be determined based on qualifications, experience and location.