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Design Engineering Manager

GlobalFoundries

On-site
Austin, TX
Full-time
Manager
$167k–$290kPosted 48m ago

Real job — pulled straight from GlobalFoundries’s careers page · Verified September 7, 2026 · No reposts.

Job description

GlobalFoundries is hiring a Design Engineering Manager — a full-time, based in Austin, TX role ($167k–$290k). Apply directly on GlobalFoundries's careers page below.

DMTS Design Engineering

Location: USA - Texas - Austin

Time Type: Full time

Job Description

The Design Manager – Smart Analog & Sensors will lead the architecture, design, and execution of complex mixed-signal SoCs, with primary focus on digital subsystem design, IP integration, and end-to-end SoC realization for sensing-driven applications.

This role emphasizes SoC creation, compute + control integration, and scalable IP-based development, enabling smart sensing platforms for automotive and industrial markets. The analog/sensor content is treated as a system integration component, while the core leadership spans digital architecture, RTL design, and SoC integration.

Role Overview

The Design Manager – Smart Analog & Sensors will lead the architecture, design, and execution of complex mixed-signal SoCs, with primary focus on digital subsystem design, IP integration, and end-to-end SoC realization for sensing-driven applications.

This role emphasizes SoC creation, compute + control integration, and scalable IP-based development, enabling smart sensing platforms for automotive and industrial markets. The analog/sensor content is treated as a system integration component, while the core leadership spans digital architecture, RTL design, and SoC integration.

Key Responsibilities

1. SoC Architecture & Digital Design Leadership

  • Define and drive SoC architecture for Smart Sensor platforms:

    • Compute subsystems (MCU / DSP / AI accelerators)

    • Interconnects (NoC, bus fabrics)

    • Memory subsystems and hierarchy

    • Control, security, and safety islands

  • Lead top-level SoC integration, partitioning functionality across digital, analog, and software domains

  • Drive hardware/software co-design, aligning system architecture with firmware and application requirements

2. IP Strategy & Integration

  • Own development, selection, and integration of internal and 3rd-party IP, including:

    • Processor cores (e.g., RISC-V / MCU-class cores)

    • DSP / ML accelerators

    • Peripherals and connectivity IP

  • Define IP reuse strategy and platformization across multiple programs

  • Ensure robust IP qualification, integration methodology, and interoperability verification

3. RTL Execution & Design Quality

  • Lead teams responsible for:

    • RTL micro-architecture and implementation

    • Subsystem integration and top-level assembly

  • Drive design best practices:

    • Lint, CDC, RDC, low-power intent (UPF)

    • Synthesis and timing closure alignment with PD

  • Ensure high-quality handoff to DV, DFT, and Physical Design teams

4. End-to-End SoC Program Execution

  • Own delivery from specification → RTL → integration → tapeout → silicon bring-up

  • Partner closely with:

    • Design Verification, DFT, PD, and product engineering

    • System architecture and applications teams

  • Drive closure on:

    • Functional correctness and coverage

    • PPA (power, performance, area)

    • Silicon bring-up readiness and debug strategy

  • Align execution with system-level modeling and requirements definition flows

5. Smart Sensor System Integration

  • Integrate analog/sensor subsystems (AFE, RF, data converters) into digital SoC framework

  • Drive system-level tradeoffs:

    • Data path partitioning (analog vs digital vs software)

    • Latency, power, and accuracy optimization

  • Ensure seamless interaction between sensor front-end, compute, and software stack

Expected Salary Range

$166,500.00 - $290,000.00

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at usaccommodations@gf.com and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address. 

 

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations. 

 

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory. 

 

All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law 

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Frequently asked questions

What is the salary for Design Engineering Manager at GlobalFoundries?

The estimated salary range for Design Engineering Manager at GlobalFoundries is $167,000 - $290,000 USD per year.

What is the seniority level for Design Engineering Manager at GlobalFoundries?

Design Engineering Manager at GlobalFoundries is a Manager level position.

How do I apply for Design Engineering Manager at GlobalFoundries?

You can view the full description and apply for Design Engineering Manager at GlobalFoundries on EchoJobs: https://echojobs.io/job/globalfoundries-dmts-design-engineering-hpyu5.