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Ethernovia

Senior Physical Layer Design Engineer

Utrecht, Netherlands
PLL RTL Verilog C++ Python Ethernet
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Description

Senior PLL Design Engineer

Location: Utrecht, The Netherlands

Department: Engineering

About Ethernovia, Inc.

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications. 

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date:

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.

With talented employees on 4 continents, we have filed 50+ patents to date.

Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.

Senior PLL Design Engineer

Summary:

  • Ethernovia is a global 7+ year-old silicon solutions provider for Automotive Ethernet with a HQ in Silicon Valley.
  • We are growing our Mixed-Signal design team, which is based in Zeist, The Netherlands.
  • We have a full-time opening for a Senior PLL designer who will work on-site in a team using advanced CMOS processes
    • Driving the architecture and implementation of advanced PLLs (with challenging performance & efficiency specifications).
  • The work typically spans the planning & execution of a full design cycle from;
    • Specification, via study & design, test-chips and their evaluation, all the way to qualification and production.
    • All this not only in close collaboration with the Analog Front-End design and Layout teams, but also with the DSP, Digital, Firmware, and System teams, as well as Marketing & FAEs.
  • This obviously requires a strong team-player mentality of all involved, so expect professional colleagues with a focus on the end-goal, as well as the needs of team-members to reach it.
  • Furthermore, we are a growing and flexible start-up company which stimulates employees to broaden their experience & skills by learning new & exciting design challenges.

Skills & Qualifications:

  • A MSc or PhD degree in Electrical Engineering (EE)
  • At least 8 years of experience in PLL design in advanced CMOS nodes
    • Preferably also experience with RTL, Verilog, C++ & Python
  • Experience in the domain of Ethernet AFEs is a plus
  • Team player with experience working in Mixed-Signal IC design teams
  • Excellent communication skills
  • Fluent in English
  • Located in: Utrecht, The Netherlands or willing to locate to the Netherlands

What we offer:

  • A full-time and indefinite contract
  • A competitive package (incl. stock option plan)
  • 25 vacation days per year and annually one extra day with a maximum of 30 days
  • A fast-growing organization with excellent career and development opportunities
  • An open organizational culture where inputs from each are valued
  • An international environment with international colleagues and development sites on four continents

#LI-Onsite

Ethernovia
Ethernovia

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