Principal Design Verification Engineer

About Etched 

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real time video generation models and extremely deep chain-of-thought reasoning. 

Title: Principal Design Verification Engineer 

Job Duties: 

Develop ASIC testbenches using advanced verification methodologies such as UVM to verify the correct functionality of microchip design. 

Implement micro-architecture and RTL specifications using System Verilog and maintain the verification environment for the specialized AI microchips, considering system-level test scenarios and coverage plans. 

Execute functional and performance verification of microchip design, employing synthesized netlists, coverage models, and tools such as Synopsys VCS and Verdi. Work in close collaboration with the design and architecture teams to ensure the design meets all functional and performance requirements. 

Apply static and dynamic methods to ensure design timing closure. This includes running static timing analysis tools, analyzing the results, and identifying solutions. 

Utilize formal verification tools for equivalence checking between RTL and gate-level netlists of microchip design. Interpret the results, identify any mismatches and work with the design team to correct them. 

Define and implement assertions and checkers at module and chip-level to ensure correct functionality and signal integrity of microchip design. 

Perform debugging of microchip using waveforms and log files and collaborate with the design team to address the root causes of any identified issues. 

Write scripts and utilities to automate various verification tasks. Employ programming languages such as Python to automate testbench generation, test case generation, and results analysis. Participate in meetings related to the verification of the microchip. Understand issues related to the design verification. Take responsibility to follow up on any required actions based on the verbal description of the work required. 

Document and present the verification plan, progress towards the plan, and coverage analysis for design signoff. Write reports on the verification process and maintain up-to-date documentation for all aspects of verification. 

Minimum Requirements: 

Master’s degree or foreign equivalent degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field and 3 years of work experience as Hardware Engineer II, Hardware Engineer III, Silicon Engineer III, Sr. Silicon Engineer, ASIC Design Verification Engineer, Staff Design Verification Engineer, Principal Design Verification Engineer, or a related occupation required. 

The required work experience must include 2 years of experience with the following: 

UVM (Universal Verification Methodology); 

Testbench development; 

EDA tool: Synopsys VCS; 

System Verilog; 

AXI (Advanced eXtensible Interface); and 

ASIC Development. 

Additional Information: 

Employer’s name: Etched.ai, Inc. 

Job site: 20401 Stevens Creek Blvd., Cupertino, CA 95014 

Salary Range: $192,000.00 per year to $250,000.00 per year 

If you are interested in applying for this position, please email resume with Job # 20230503 to jobs@etched.ai 

How we’re different: 

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. 

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. 

Benefits: 

Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents

Housing subsidy of $2,000/month for those living within walking distance of the office

Daily lunch and dinner in our office 

Relocation support for those moving to Cupertino