Frontend CAD Intern

Join our Team

Sponsorship: Ericsson Inc. does not sponsor US work authorizations for this job position including H-1B, O-1, L-1, and TN. Ericsson also does not hire F-1’s working on EAD for this position. 

Position: Frontend CAD Intern
Location: Austin, Texas
 

About this opportunity:

To excel in this high-visibility role, we seek individuals with an interest in ASIC IP/ASIC SoC development, a profound interest in system-on-chip design & verification and a deep interest in methodologies and tools increasing efficiency of our global engineering community. 
As a key member within the Frontend CAD (FE CAD) department, you'll play a crucial role in shaping and optimizing methodologies and EDA workflows, ensuring seamless adoption of industry best practices for crafting efficient System on Chips (SoCs).
The ideal candidates is driven by solving new technical challenges, good at identifying areas for improvement in methodologies, tools, and support structures, have a keen interest in learning new skills, and are dedicated to continuous improvement, you might be the perfect fit for us, contribute to our dynamic team and shape the future of our silicon design endeavors.

What you will do:

•    Collection and storage of raw data in a centralized DB
•    Experiment with different visual representation of big data.
•    Build and maintain relationships with Project, Program, and engineering stakeholders, ensuring alignment with project goals and timelines.
•    Facilitate effective communication and collaboration among these groups.
•    Demonstrate strong troubleshooting and critical thinking skills to identify and address technical challenges during the silicon design process.
•    Implement processes for ensuring the quality of silicon design, including rigorous design reviews, testing methodologies, and quality assurance practices.
 

The skills you bring:

•    Pursuing a Master of Science or Bachelor of Science, Electrical Engineering, Computer Science, or similar
•    Attained a junior level of college coursework
•    Exposure to ASIC IP/ASIC SoC design, RTL, Verilog, UVM, and System Verilog.
•    Familiarity with front-end tools including Verilog simulators, RTL/Verification linters, clock domain crossing checkers.
•    Practical experience in scripting languages such as Perl, Python, bash, csh, etc.
•    Background in visualization of data via Power BI or some other tool.
•    Familiarity with databases such as mySQL, MongoDB, etc
•    Completed at least 2.5+ years of Engineering or Computer Science coursework.
 

This position is accepting applications until November 30, 2024 for the Summer 2025 or until filled