Engineering Manager - Silicon Design

Join our Team

About The Opportunity 

Are you ready to drive and shape the future of Ericsson Silicon’s methodology and tools? Join our dynamic team within the newly established Frontend CAD department, dedicated to defining methodologies and EDA workflows across our global R&D sites located in Austin, Stockholm, and Lund. The Team is part of the Ericsson Silicon engineering unit, which develops state of the art ASIC's and FPGA's for Ericsson's 5G and 6G product portfolio. The department offers many opportunities for career growth and a large base of knowledge to learn from.

To be successful in this high visibility role we see that you have a background within ASIC IP/ ASIC SoC development and a big interest in system-on-chip design & verification. Ericsson Silicon is working with the latest technology nodes and FE CAD department is responsible for optimizing and crafting our Silicon design methodology and tools to ensure our silicon is optimized for speed, area, and power. We see that you are passionate about solving new technical problems and are interested in learning new skills and always improving yourself.

The role involves driving excellence in ASIC IP/ASIC SoC development by supporting and enhancing methodologies, tools, and workflows for optimal system-on-chip design and verification. Focusing on technical collaboration, efficient support systems, and a passion for tackling technical challenges makes this position ideal for individuals committed to innovation and continuous improvement.

What You will do 
•    Participate in the day-to-day development and support of complex tool flows in Frontend Design & Verification.
•    Ensure healthy relationships with EDA vendors, guaranteeing the success of Ericsson programs and excellent Application Engineering support.
•    Maintain and update EDA project tool versioning and compatibility.
•    Build and maintain relationships with Project, Program, and engineering stakeholders, meeting their needs.
•    Collaborate with Central Silicon Infrastructure to provide a stable environment for our Engineers, focusing on LSF, Linux access, disk performance, RHEL versioning, and optimized compute nodes for EDA workloads.
•    Lead and develop a high-performance engineering team

Skills you bring; 

•    Deep expertise in ASIC IP/ASIC SoC design, Verilog, and System Verilog.
•    Proficiency in front-end tools (Verilog simulators, linters, clock domain crossing checkers)
•    Familiarity with synthesis, static timing analysis, DFT.
•    Knowledge of System-Verilog assertions, checkers, and additional design verification techniques are advantageous.
•    Familiarity in scripting languages like Python etc.
•    Extensive understanding of modern silicon design techniques.
•    Experience in leading, coordinating and supporting geographically dispersed engineering teams.
•    Strong communication and presentation skills.
•    Master of Science, Electrical Engineering, Computer Science, Physics or similar with 10+ years of experience
•    Self-driven with the ability to manage high engineering support loads across multiple teams located in Stockholm and Lund