Real job — pulled straight from Efficient Computer’s careers page · Verified September 7, 2026 · No reposts.
Job description
Efficient Computer is hiring a Senior Digital Verification Engineer — a full-time, based in San Jose, CA role ($160k–$210k). Apply directly on Efficient Computer's careers page below.
Staff Digital Verification Engineer
Location: San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX
Department: Verification & Emulation
Efficient Computer is rethinking computing from the ground up to solve one of AI's biggest challenges: energy. Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. With our first processor, Electron E1, now shipping in volume and more than $97 million in Series B financing recently announced, we're accelerating customer deployments and scaling our architecture to data center performance. Join us to build the hardware and software that bring intelligence wherever it's needed and help shape the next generation of computing.
We are looking for an experienced Staff Design Verification Engineer to drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team. This is a great opportunity to have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Required Qualifications & Experience
- Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
- UVM and SystemVerilog: Expertise in UVM-based testbench architecture and constrained-random verification methodology
- C/C++ experience for modelling or verification.
- Coverage Closure: Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
- Debug Skills: Proven ability to debug complex simulation failures.
- Scripting & Automation: Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
- Communication: Ability to clearly communicate verification risk, status and tradeoffs to technical peers and program leadership.
Ways to stand out :
- Experience in Formal verification (JasperGold or similar).
- Experience building or using AI Agentic flows for DV.
- Software/Firmware based testing experience and working with software teams pre-silicon
- Post-silicon experience
- SoC Architecture: Understanding and experience in some of the following areas : processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
- Power aware verification and UPF
We offer a competitive base salary for this role, generally ranging from $160,000 to $245,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
Why Join Efficient?
Build what's next. At Efficient, you'll tackle big challenges with room to take ownership and make an impact. We back you with competitive pay, equity, a 401(k) match, company-paid benefits, paid parental leave, and flexibility—plus opportunities to grow your skills and career as we scale.
Get Senior Digital Verification Engineer jobs like this→
New roles from thousands of companies land hourly, straight from their careers pages. Get the freshest matches by email so you never miss one.
Email me new jobsSimilar jobs
Frequently asked questions
What is the salary for Senior Digital Verification Engineer at Efficient Computer?
The estimated salary range for Senior Digital Verification Engineer at Efficient Computer is $160,000 - $210,000 USD per year.
What skills are required for Senior Digital Verification Engineer at Efficient Computer?
The required skills for Senior Digital Verification Engineer at Efficient Computer include: SystemVerilog, C++, Python, ARM.
What is the seniority level for Senior Digital Verification Engineer at Efficient Computer?
Senior Digital Verification Engineer at Efficient Computer is a Senior level position.
How do I apply for Senior Digital Verification Engineer at Efficient Computer?
You can view the full description and apply for Senior Digital Verification Engineer at Efficient Computer on EchoJobs: https://echojobs.io/job/efficient-computer-senior-digital-verification-engineer-0vkos.