Senior Compiler Engineer

Location: San Jose, CA OR Pittsburgh, PA

Department: Compiler

We are seeking a Senior Compiler Engineer to join our growing team. The Compiler Engineer will contribute to the design and implementation of an embedded machine learning (ML) system stack and TinyML applications to run on the world’s most energy-efficient programmable processor. This position is a unique opportunity to develop applications for cutting-edge hardware as part of a highly interdisciplinary team, helping to demonstrate the value of Efficient’s breakthrough technology. If you are an engineer who wants to be part of an intensely skilled team and wants to have an immediate impact building the next generation of energy-efficient ML applications, we want to talk with you!

Key responsibilities

• Develop new compiler features to improve overall hardware efficiency while maintaining programmability. These may relate to:
  - Efficient’s new dataflow ISA
  - Memory analysis and ordering Hardware constraints such as timing and power consumption
  - Place-and-route of applications onto Efficient’s fabric
  - Visualization
  - Programmer debugging tools
• Write unit and integration tests to uncover functional- and performance-related compiler bugs.
• Work with various machine-learning frameworks to compile models to our custom hardware.
• Debug and fix functional and performance issues of the compiler system.
• Collaborate with the hardware and physical design team to understand and improve hardware architecture and propose future improvements.
• Work closely with the application development team to understand the problem domain and deliver optimized compiler solutions.

Required qualifications & experience requirements

• 6+ years of experience with C++.
• Bachelor's/Master's degree in CS or related field.
• Familiarity with compiler frameworks such as GCC, LLVM, and/or MLIR.
• Understanding of computer architecture and optimization.
• Experience using industry standard development and debugging tools including GDB.
• Strong attention to detail, good work ethic, ability to work on multiple projects simultaneously, and good communication skills.
• Good problem solving skills.

Additional qualifications considered

• Familiarity with FPGA-compilation and/or PnR algorithms.
• Experience with verilog, system verilog, or VHDL.
• Knowledge of computer architecture.

We offer a competitive salary for this role, generally ranging from $160,000 to $210,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.