Physical Design - SOC Top Lead

Location: San Jose, CA OR Pittsburgh, PA OR Austin, TX

Department: Physical Design

We're looking for a Lead Physical Design Engineer to take end-to-end ownership of SOC -top for our next-generation SoCs. This is a hands-on, high-accountability role — you'll be the single point of ownership driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You'll work closely with block-level PD owners, DFT, package/IO teams, and the architecture team. This role will be in the newly formed hardware engineering group and will focus on designing in state of the art finfet technologies.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Full-chip integration: floorplanning, power planning, macro/hard-IP placement, and block partitioning at the top level, ensuring convergence across all hierarchical blocks
• Timing closure: full-chip STA across all corners/modes (setup, hold, OCV, multi-mode multi-corner), including cross-boundary timing and chip-level constraint (SDC) ownership
• Power: full-chip power planning, PDN design/analysis (IR drop, EM), rail architecture, and coordination on power-gating strategy with block owners
• Physical verification: DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles across blocks
• Signal integrity & noise: crosstalk, di/dt, and chip-level noise closure, especially around high-speed IO and PLL/analog boundaries
• Clock & reset architecture: top-level clock tree strategy across domains, including CTS coordination with block owners
• DFT integration: chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead on ATPG/test coverage closure at full-chip level
• Package/IO co-design: bump/ball map coordination, IO ring planning, and package-aware floorplanning
• Tapeout readiness: sign-off checklist ownership (timing, power, physical, reliability) and final GDS handoff
• Cross-team coordination: single point of contact between block-level PD owners, DV, DFT, package engineering, and architecture on all convergence-related tradeoffs and schedule risk
• Technical leadership: mentor block-level PD engineers on convergence best practices; set methodology and flow standards for chip-top closure across the program.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• 8-12+ years of physical design experience, with at least 2-3 full tapeouts at the chip-top/SoC integration level (not just block-level)
• Deep hands-on experience with advanced nodes
• Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
• Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
• Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
• Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map) is a plus
• Tool fluency: Innovus (or ICC2), Tempus/PrimeTime, RedHawk, Calibre
• Demonstrated ability to lead technically without direct reports — driving alignment across multiple engineers and teams on convergence decisions
• Comfortable operating with significant ownership and ambiguity in a small, fast-moving team — this isn't a role where you hand off convergence problems, you solve them
• Experience with non-standard/novel architectures (dataflow, tiled, NoC-based) is a plus but not required
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements 

• Knowledge of computer architecture
• Knowledge of physical design and ASIC implementation
• Experience in full chip sign off convergence
• Knowledge of circuit design, device physics, deep sub-micron technology and its implications to physical design
• Proficiency with industry-grade physical design flow.
• Experience in integrating analog or mixed-signal macro on top-level design.

We offer a competitive salary for this role, generally ranging from $200,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.