Performance Research Engineer (multiple levels)

Location: San Jose, CA OR Pittsburgh, PA

Department: Optimization

About the Role

We are seeking Performance Research Engineers (staff to principal levels) to join our growing team. Efficient’s Performance Research Engineers research new optimization techniques; design new tools for AI assisted optimization and performance analysis; collaborate with our architecture team on the design of future hardware; design and perform modeling experiments using our architecture simulator; and collaborate with our world class compiler team, evaluating code-generation quality, suggesting new intrinsics, influencing the ISA, and experimenting with new language extensions. This is an applied research role, where you will be asked to drive the integration of these new techniques, tools, and language extensions into our existing performance libraries. 

This position is a unique opportunity to work on cutting-edge hardware/software co-design, while making an immediate impact on building the next generation of performance libraries, applications, and hardware used by our customers.

Required Qualifications & Experience

• Hands-on software development experience working closely with hardware, including exposure to at least two RISC, DSP or GPU platforms.
• A passion for understanding and addressing performance issues that are unique to our Fabric dataflow architecture.
• Experience with framework and library design, particularly within resource constrained and realtime environments.
• Experience with CUDA, HIP and/or other parallel programming models.
• The ability to lead and work independently.
• A collaborative spirit, with the ability to work with and influence multiple engineering teams.
• Demonstrated ability to write, debug, and maintain low-level, C/C++, systems-level code as well as design clean interfaces and modular code.
• Actively uses AI tools to generate, optimize, and debug code.
• Familiarity with low-level programming interfaces, e.g. PTX, LLVM IR and/or MLIR. 
• Experience working with HW simulation environments.
• Domain expertise in three or more of the following areas: Linear Algebra, ML, Image Processing, Video Processing, Signal Processing, Audio Processing, SDR, realtime programming, or Robotics.
• Background in performance profiling, benchmark design, or comparative hardware analysis.
• Excellent written, verbal, analytical and technical communication skills, with the ability to clearly document complex systems, lead discussions across teams, as well as the ability to drive consensus across teams.
• Minimum Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field. PHD preferred. Equivalent work experience.

Desired Qualifications & Experience

• • Some experience working on compiler development.
  • Some experience working with high-performing HW architecture teams.

We offer a competitive salary for this role, generally ranging from $180,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.