Real job — pulled straight from E-Space’s careers page · Verified July 19, 2026 · No reposts.
Job description
E-Space is hiring a Senior Static Timing Analysis Methodology Engineer — a full-time, based in Saratoga, CA role ($120k–$220k). Apply directly on E-Space's careers page below.
Senior Static Timing Analysis (STA) Methodology Engineer
Team: Engineering & Operations
Location: Saratoga, CA
Commitment: Full-Time
Workplace Type: onsite
Salary:
WHAT YOU WILL BE DOING:
• Lead cross-functional efforts to solve complex timing challenges across multiple IPs, projects, and technology nodes
• Develop and enhance STA methodologies across the full RTL-to-GDS flow, including early timing estimation, feasibility checks, synthesis and place-and-route optimization, signoff criteria, and post-route ECO strategies
• Architect, optimize, and maintain production STA flows using industry-standard EDA tools, continuously improving PPA and runtime efficiency
• Drive signoff correlation and closure using PrimeTime and related tools (PT-SI, PTPX, PT-ECO)
• Debug timing constraints, resolve timing correlation issues, and develop effective timing closure strategies
• Explore and deploy data-driven and ML-assisted techniques to improve STA automation, predict and prioritize timing risk, and guide optimization across blocks and full-chip
• Design, implement, and maintain scalable CAD utilities and STA flow components that improve PPA, robustness, and team productivity
• Continuously refine workflows and introduce new technologies to ensure robust, PPA-optimized timing solutions across all product lines
• Provide timing closure guidance and mentorship to design and physical design engineers
WHAT YOU BRING TO THIS ROLE:
• BS or MS in Electrical or Computer Engineering, or equivalent industry experience
• 8+ years of industry experience in STA and timing methodology, focused on high-performance and low-power designs at advanced technology nodes
• Deep knowledge of STA tools and techniques, including noise, crosstalk, OCV, AOCV, POCV, and LVF analysis
• Fluency with PrimeTime and related signoff tools (PT-SI, PTPX, PT-ECO), with extensive hands-on experience driving signoff correlation and closure
• Strong expertise in debugging timing constraints and resolving timing correlation issues across complex SoC designs
• Experience with MMMC analysis, timing ECO flows, and late-stage timing closure techniques
• Proficiency in writing robust, production-quality scripts in Tcl, Python, and/or Perl for CAD utilities and flow components
• Solid knowledge of clock tree synthesis (CTS) and its interaction with timing analysis
• Excellent communication and collaboration skills for cross-functional, multi-project environments
BONUS POINTS:
• Experience with advanced process nodes (7nm, 5nm, or below)
• Familiarity with low-power design methodologies and their timing implications (DVFS, power gating)
• Exposure to interface protocol timing (DDR, PCIe, USB, SerDes)
• Experience applying ML or data-driven methods to EDA flow optimization
• Background in satellite communication, 5G, or IoT SoC design
Get Senior Static Timing Analysis Methodology Engineer jobs like this→
New roles from thousands of companies land hourly, straight from their careers pages. Get the freshest matches by email so you never miss one.
Email me new jobsSimilar jobs
Frequently asked questions
What is the salary for Senior Static Timing Analysis Methodology Engineer at E-Space?
The estimated salary range for Senior Static Timing Analysis Methodology Engineer at E-Space is $120,000 - $220,000 USD per year.
What skills are required for Senior Static Timing Analysis Methodology Engineer at E-Space?
The required skills for Senior Static Timing Analysis Methodology Engineer at E-Space include: Python, Perl.
What is the seniority level for Senior Static Timing Analysis Methodology Engineer at E-Space?
Senior Static Timing Analysis Methodology Engineer at E-Space is a Senior level position.
How do I apply for Senior Static Timing Analysis Methodology Engineer at E-Space?
You can view the full description and apply for Senior Static Timing Analysis Methodology Engineer at E-Space on EchoJobs: https://echojobs.io/job/e-space-senior-static-timing-analysis-sta-methodology-engineer-qodl6.