Senior Digital Backend (Place & Route) Layout Engineer

What you will be doing:

• Physical Implementation: Manage end-to-end backend physical design flow, including floor planning, placement, routing, and timing optimization
• Power and Performance Optimization: Optimize layout for power efficiency, timing closure, and area, ensuring alignment with project specifications and industry standards
• Timing Analysis and Closure: Perform Static Timing Analysis (STA) and drive timing closure, working collaboratively with frontend and verification teams
• DRC/LVS Compliance: Ensure designs are DRC (Design Rule Check) and LVS (Layout Versus Schematic) compliant using industry-standard tools
• Tool Utilization and Scripting: Proficiency with industry-standard EDA tools for P&R, STA, and verification (e.g., Cadence Innovus, Synopsys ICC2, Mentor Calibre) and scripting languages (e.g., TCL, Python, Perl) for flow customization and automation
• Cross-functional Collaboration: Work closely with digital design, verification, and RF/analog layout teams to ensure successful integration of all components
• Documentation and Reporting: Maintain accurate and up-to-date documentation of design methodologies, processes, and results, reporting to project leads and management

What you bring to this role:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 5+ years in digital backend design, with a strong track record of successful P&R and tape-out in advanced process nodes (e.g., 7nm, 5nm)
• Proficiency with physical design tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, etc.
• Strong knowledge of timing analysis, clock tree synthesis, IR drop analysis, and EM checks
• Familiarity with physical verification techniques, including DRC, LVS, and PEX
• Scripting experience with TCL, Python, or Perl for tool automation
• Strong verbal and written communication skills to collaborate across teams and present complex technical concepts effectively