Senior 5G MAC Software Engineer

Team: Engineering & Operations

Location: Santa Clara, CA

Commitment: Full-Time

Workplace Type: onsite

What you will do:

Own the software architecture, redesign, implementation, and integration of MAC-side software for a new 5G NR physical layer, including PHY integration, emulation, and test capabilities.
Define a portable, layered architecture that separates MAC behavior, the MAC-PHY interface, platform transport, and operating-system services. Support host-based simulation, execution on a simulated ARM processor, and deployment on FPGA and ASIC platforms.
Define and evolve the MAC-PHY interface, including message sequencing, timing, buffer ownership, compatibility, versioning, and error handling. Coordinate changes with PHY and protocol-stack engineers.
Implement and debug real-time control and data flows for terrestrial 5G NR, including PDCCH, PDSCH, PUSCH, PUCCH, PRACH, SRS, HARQ, CQI, timing advance, and measurements.
Design low-power communication between ARM software and PHY firmware using shared memory, mailboxes, interrupts, and efficient data movement. Address concurrency, cache coherency, memory ordering, backpressure, timeouts, and recovery.
Extend the SystemC TLM virtual platform, with guidance from system designers, and carry the software through FPGA and ASIC integration. Debug system-level failures on simulated and physical SoCs.
Build automated regressions, test-vector flows, traces, and KPI checks that correlate behavior across simulation and hardware.
Review architecture and code, coordinate dependencies across software, firmware, systems, verification, and hardware teams, and gradually expand into production MAC development.

What you bring to this role:

Demonstrated experience architecting and delivering embedded C/C++ software for a wireless modem, baseband, or comparable real-time, resource-constrained system.
Practical knowledge of 5G NR MAC and relevant 3GPP specifications, including terrestrial operation, scheduling, HARQ, random access, and MAC-PHY interactions.
Hands-on experience debugging heterogeneous SoCs and hardware-software interfaces involving shared memory, mailboxes, interrupts, DMA or similar data movement, cache coherency, and multicore synchronization.
Experience developing embedded Linux software and working with an RTOS.
Working knowledge of digital communications and DSP sufficient to understand PHY processing constraints, timing, and data flow.
Ability to decompose complex systems into clear components and interfaces, make sound architectural tradeoffs, diagnose integration failures, and collaborate effectively across software and hardware teams.
A track record of independent technical ownership, supported by reproducible tests, version control, and clear design documentation.
Typical background: BS with 7+ years, MS with 5+ years, or PhD with 3+ years of relevant experience in wireless communications, embedded software, computer engineering, or a related field. Equivalent demonstrated expertise is also welcome; these are guidelines rather than mandatory minimums.

Bonus points for the following:

Experience modifying SystemC TLM virtual platforms or integrating production software with virtual hardware models.
Experience taking embedded modem software through FPGA prototyping, pre-silicon verification, ASIC bring-up, and hardware correlation.
Experience designing or extending a MAC-PHY interface such as FAPI, nFAPI, or a proprietary equivalent.
Experience with Zephyr, FreeRTOS, vector DSPs, or heterogeneous ARM and DSP SoCs.
Experience optimizing modem or baseband software for low power.
Experience with 5G NR non-terrestrial networks, including propagation delay, timing advance, Doppler-related coordination, or NTN scheduling and HARQ.
Experience contributing to production protocol-stack software, including MAC, RLC, RRC, or a MAC-PHY adaptation layer.

Additional Requirements

This is a fast-paced, high-impact environment - flexibility to occasionally work extended hours or weekends during critical periods is expected.