Senior Power Integrity Engineer
Location: Raanana
#LI-Hybrid
About Us:
DriveNets is leading the way in high-performance network and communication solutions. Our products power the next generation of Ethernet routers and cutting-edge technologies, delivering unparalleled reliability and performance in the most demanding environments. We strive to solve complex power integrity challenges to ensure the highest quality and performance in our designs.
The Role:
We are looking for an experienced Senior Power Integrity Engineer to join our Hardware Engineering team. This role will be critical in establishing power integrity guidelines, recommending supply noise design solutions, conducting IR drop and VRM performance analysis, and ensuring optimal power distribution across our high-speed platforms. As part of the team, you will also assess the effectiveness of PCB decoupling solutions and develop power integrity models.
Responsibilities:
• Establish and implement power integrity guidelines for high-speed electronics.
• Select & Conduct IR drop and voltage regulator module (VRM) performance analysis to ensure reliable power distribution.
• Develop power integrity models based on measurement data to optimize power delivery.
• Analyze and design for optimal PCB decoupling strategies to mitigate noise and ensure stable power delivery across the board.
• Perform simulations and analysis on power noise, current profiles, and supply voltage integrity.
• Perform power noise and jitter simulations to assess the impact of power delivery on signal integrity.
• Use tools like Ansys SIWAVE, Cadence Sigrity and similar to analyze and simulate power integrity across high-speed platforms.
• Bachelor's or Master’s degree in Electrical/Electronics Engineering with 10+ years of relevant experience.
• Strong knowledge of power integrity principles and methodologies for high-speed electronic platforms.
• Hands-on expertise in static and dynamic IR drop analysis and power integrity simulations.
• Experience working with high-speed interfaces such as 112Gbps PAM4 Ethernet, PCIe Gen5, DDR5, etc.
• Proficiency in CAD tools such as Cadence Allegro or equivalent for power integrity analysis.
• In-depth experience with power noise, jitter simulations, and current profile usage (Icc).
• Experience using EDA tools for power integrity analysis.
• Strong background in developing power integrity models based on measurement data.
• Experience with PCB and package layout techniques, particularly for power delivery and decoupling solutions.
Advantages:
• Knowledge of SSO (Simultaneous Switching Output) simulation techniques.
• Familiarity with high-speed PCB design, especially for power delivery and decoupling strategies.
• Expertise in power noise and jitter simulation for high-speed interfaces.
• Experience with advanced power integrity simulation tools.
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