Chip Level STA Engineer

Location: Armenia

Remote Type: Onsite Only

Time Type: Full time

Job Description

Meet the Team 

Join Cisco’s ASIC Physical Design Team, where we ensure the highest quality in full-chip timing closure and circuit performance to guarantee a successful tape-out. We bridge the gap between design and reality by collaborating across block implementation, flow, SDC, EMIR, and IP/tool vendor teams to drive silicon excellence. As a tight-knit group of highly skilled engineers, we foster a collaborative environment where innovation meets precision. Together, we are building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project. This is your opportunity to shape the technology that connects the world while working alongside a team that values mentorship and celebrates technical success.

Your Impact

Drive Cisco's silicon innovation by ensuring high-performance timing closure and rigorous sign-off for our next-generation chips to guarantee a successful tape-out. Analyze full-chip timing and design rule violations to identify root causes and implement effective solutions that maintain design integrity. Develop robust timing closure methodologies for block and top-level designs to streamline development and improve efficiency. Collaborate closely with implementation teams to ensure smooth ECO execution and seamless design handoffs. Evaluate complex clocking structures and timing constraints to guarantee that all silicon solutions meet stringent performance targets.

Minimum qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Science.

• Minimum of 3 years of hands-on experience in ASIC design and verification.

• Proven experience working with deep submicron CMOS technologies.

• Comprehensive knowledge of the full design cycle from RTL to GDSII.

• Demonstrated hands-on experience in RTL2GDS flows, floorplanning, and power planning.

Preferred qualifications

• Demonstrated hands-on experience in Static Timing Analysis (STA) and timing closure.

• Advanced understanding of timing derates, variations, and complex design constraints.

• Experience with standard cell timing characterization.

• Proficiency in generating timing ECOs and resolving complex timing violations.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you.