ASIC Engineering Technical Leader

Location: Taipei, Taiwan, Hsinchu, Taiwan

Remote Type: Hybrid

Time Type: Full time

Job Description

Develop test vehicle strategy and design for advanced package technologies with 2.5D/3D integration stacking process.

• Engage with leading assembly suppliers to understand assembly process, module design rules and requirements.
• Define assembly process integration and flow for advanced heterogeneous integration including Co-packaged Optics and Co-packaged Copper package integration solution.
• Develop comprehensive plan to evaluate and qualify new package technologies.
• Work closely with substrate suppliers to evaluate new materials & design rules for package warpage, stress, and SI/PI performance optimization to enable and advance product substrate physical design and implementation.
• Work with internal package physical design team to resolve design challenges and implement working solutions using DfM/DfR principles.
• Work with OSAT and substrate suppliers to develop practical solutions that address challenges of large body size package and large die reticle size assembly, reliability and board-mount process.

This is a critical role where you will directly influence the technical direction and successful delivery of Cisco’s advanced products by driving innovative packaging and assembly solution.

Minimum Qualifications

• BS/MS/PhD in Mechanical Engineering, Materials Science, Physics or a closely related field 
• 10+ years of progressive experience in Semiconductor Packaging and Assembly Industry, with demonstrated skill and experience leading technical projects or initiatives
• Previously proven experience in advanced packaging technology development and execution, such as 2.5D/3D process integration, heterogenous integration, wafer-level packaging, and package technology qualification method.
• Comprehensive knowledge and understanding of advanced CoWoS package assembly and manufacturing flow.
• Good understanding of Co-packaged Optics and Co-packaged Copper design and process integration
• Previous experience with substrate manufacturing processes, design rules and material for high layer count substrate stack-up including multi-layer core technology and impacts to device level power and signal integrity.
• Experience with package design physical attribute, material selection and package assembly process optimization for package warpage, stress and thermal performance. 

Preferred Qualification

• Expertise in advanced problem-solving methodologies (e.g. 8D, FMEA, statistical process control) and data analysis skills

• Effective communication, presentation, and influencing skills, with the ability to articulate technical concepts clearly to diverse audiences.
• Experience in package reliability for component and board level
• Willingness to learn and evolve professionally.

We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Why Cisco? 

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. 

We are Cisco, and our power starts with you.