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Senior Verification Engineer

Ceva

On-site
Belgrade, RS
Full-time
Senior
5+ yrs
Salary not listedPosted 2mo ago

Real job — pulled straight from Ceva’s careers page · Verified June 11, 2026 · No reposts.

Job description

Ceva is hiring a Senior Verification Engineer — a full-time, based in Belgrade, RS role. Apply directly on Ceva's careers page below.

Senior Verification Engineer

Location: Belgrade, Serbia (RS)

Experience Level: Senior

Description

About the Business Unit:

The Mobile Broadband Business Unit (MBBU) at Ceva is a leading innovation hub focused on the development of advanced Digital Signal Processing (DSP) ASIC solutions tailored for next-generation wireless communication systems. Our team drives cutting-edge projects that power infrastructure across the mobile broadband ecosystem, including 5G base stations, private networks, and emerging low Earth orbit (LEO) satellite platforms. We specialize in high-performance, power-efficient architectures that enable robust connectivity, scalable deployment, and enhanced signal processing capabilities.

 About the Role:

The VLSI verification team is responsible for producing fully verified IP, Subsystem and System environments. The role provides the opportunity to work on challenging projects, latest tools and methodologies and a scope of domains including UVM-System Verilog, System C, Formal verification and emulation.


Responsibilities:

As part of this position, you will play a central role in the verification team. Your role will include working on state-of-the-art verification environments and latest verification tools. The role requires the development of a full verification flow from architecture definition, through verification strategy, micro architecture, test plan, functional coverage plan and presentation to management.

Requirements


  • B.Sc /M.Sc. graduates in Electrical Engineering.
  • 5-8 years of experience in Verification.
  •  Hands-on experience in SystemVerilog-UVM and/or Specman.
  • Fluent in English ( verbal and written).
  • Self-motivated and self-directed, proactive.
  • Ability to achieve results in a fast moving, agile flow and dynamic environment, both locally and across the organization.
  • Great communication skills.

Advantages:

  • Knowledge in SystemC
  • Knowledge in Specman
  • Knowledge in C++
  • Usage and planning with vplan/vmanager
  • Knowledge in DSP, 5G protocols



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Frequently asked questions

What skills are required for Senior Verification Engineer at Ceva?

The required skills for Senior Verification Engineer at Ceva include: SystemVerilog, C++.

What is the seniority level for Senior Verification Engineer at Ceva?

Senior Verification Engineer at Ceva is a Senior level position.

How do I apply for Senior Verification Engineer at Ceva?

You can view the full description and apply for Senior Verification Engineer at Ceva on EchoJobs: https://echojobs.io/job/ceva-senior-verification-engineer-gd6vc.