Formal verification engineer

Location: Ra'anana, Israel (IL) (IL)

Experience Level: Intermediate

Description

About the Business Unit:

The AI Division is a unique and dedicated group within Ceva, driving innovation in Machine Learning and Generative AI architectures for edge devices and cloud inference.

Our R&D domains span Neural Network Processors (NPU), Vision DSPs, and advanced AI algorithms for applications across smartphones, tablets, automotive, surveillance cameras and many more edge AI systems.

We combine cutting-edge hardware IP design with embedded software and system-level solutions, enabling the next generation of intelligent and energy-efficient devices.

About the Role:

In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.

This role allows for independent work, impactful input, and substantial contributions to the VLSI department’s verification tasks

Responsibilities:

Develop Formal Test benches and Properties - Write and maintain System Verilog Assertions to formally verify RTL designs using industry-standard formal tools.

Collaborating with Design and Verification Teams.

Contribute to Verification Planning and Coverage.

Define formal verification plans, track progress, and contribute to achieving verification completeness.

Requirements

• Bachelor’s degree in electrical engineering.
• 3-5 years of experience in verification position.
• Proficiency in System Verilog is essential.
• A proactive, self-driven individual with problem-solving and complex analysis capabilities.
• Capable of delivering results in a dynamic, agile environment, both independently and organization-wide

Advantages:

• Practical experience with Jasper is beneficial; familiarity with SV-UVM, Python, and Tcl is advantageous.
• Experience in Formal Verification or Dynamic Verification