Virtual Protocol Architect
Location: GYEONGGI-DO (Seoul)
Time Type: Full time
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Overview:
As an architect of Cadence’s Virtual Solutions R&D team, you will develop product features used by electronics industry leaders to verify their designs and to co-develop their target AVIPs using our industry leading Palladium and Protium hardware emulators.
Specifically, you will create technology innovations in our Accelerated Verification IP product lines to solve our customers’ hardware/software co-development challenges on their leading-edge electronic designs across industries such as hyperscale and AI computing, mobile, automotive and defense/aerospace. You will work as part of a locally based team with regular interactions with a wider global team.
Job Responsibilities:
Analyze incoming customer requirements, map to product feature enhancements and present proposed solutions for review and agreement within the R&D team
Implement product features using latest RTL and C++ language standards within a significant existing product code base
Write unit and feature tests for features that you have developed
Review implementation approaches and code developed by other team members
Work within a larger cross-functional team to ensure quality and timely deliveries and deployments of product features to customers
Architect the Performance verification solution and deploy across worldwide customer base
Job Qualifications:
Bachelor's Degree with 16+ years of experience or Masters with 14+ years of experience or PhD with 10+ years of experience
Strong English verbal and written communications skills
Strong software engineering and developments skills C++/C including modern source code control environments
Experience developing software related to or using hardware communication protocols like AMBA (CHI, AXI, ACE), Gui framework tools or more generally other hardware communication protocols.
Experience using SystemVerilog HDL preferred.
Experience with simulation and/or emulation technology preferred.
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