Senior Principal Design Engineer
Location: BANGALORE 08
Time Type: Full time
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description – Verification Engineer (PCIe Design IP)
Experience: 7 to 15 Years
We are hiring motivated and passionate Verification Engineers to join our PCIe Design IP group.
Key Responsibilities
- Verify PCIe Design IP across multiple generations
- Develop and maintain SystemVerilog/UVM-based verification environments
- Collaborate closely with design, architecture, and validation teams
- Contribute to verification strategy, coverage closure, and sign-off activities
Required Skills
- Strong hands-on experience with SystemVerilog and UVM
- Solid background in functional verification of PCIe
- Good understanding of verification methodologies and best practices
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