Cadence Design Systems logo

Principal Design Engineer

Cadence Design Systems

On-site
Austin, TX
Full-time
Principal
Salary not listedPosted 2mo ago

Real job — pulled straight from Cadence Design Systems’s careers page · Verified July 4, 2026 · No reposts.

Job description

Cadence Design Systems is hiring a Principal Design Engineer — a full-time, based in Austin, TX role. Apply directly on Cadence Design Systems's careers page below.

Principal Design Engineer

Location: AUSTIN

Time Type: Full time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization.

Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

Required experience

  • Worked on Subsystem / SOC level verification projects
  • Experience in ARM based designs.
  • In-depth knowledge SV-UVM
  • Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy
  • Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals
  • Experience in C based testcase development
  • Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
  • Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
  • Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems 
  • Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
  • Experience in mentoring junior engineers
  • Self-driven and committed individual who can work in a fast paced project environment

Desirable skills and experience

  • Prior experience with Cadence tools and flows is highly desirable
  • Familiarity with ARM/CPU architectures is a plus
  • Experience in developing c-based test cases for SOC verification
  • Experience with assembly language programming
  • Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
  • Embedded C code development and debug
  • Formal Verification experience
  • Cadence verification tool experience

Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to team’s success.

We’re doing work that matters. Help us solve what others can’t.

Get Design Engineer jobs like this

New roles from thousands of companies land hourly, straight from their careers pages. Get the freshest matches by email so you never miss one.

Email me new jobs
Optiver logo

FPGA Engineer

Amsterdam, North Holland
✓ From careers page· 29m ago
Optiver logo

FPGA Internship

Amsterdam, North Holland
✓ From careers page· 29m ago
Optiver logo

FPGA Developer Intern

Shanghai, China
✓ From careers page· 29m ago
Normal Computing logo

Hardware Architect

Silicon Valley
✓ From careers page· 4h ago

Frequently asked questions

What skills are required for Principal Design Engineer at Cadence Design Systems?

The required skills for Principal Design Engineer at Cadence Design Systems include: SystemVerilog, ARM, PCIe, Ethernet, C, Assembly, I2C, SPI.

What is the seniority level for Principal Design Engineer at Cadence Design Systems?

Principal Design Engineer at Cadence Design Systems is a Principal level position.

How do I apply for Principal Design Engineer at Cadence Design Systems?

You can view the full description and apply for Principal Design Engineer at Cadence Design Systems on EchoJobs: https://echojobs.io/job/cadence-design-systems-principal-design-engineer-rggpo.