Cadence Design Systems

Principal Design Engineer

China
Python Perl
Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Principal Design Engineer – Verification

Location: Nanjing/Shanghai

Position Description:

Lead project verification. The engineer should be good at teamwork and able to help team development.

Specific duties include:

  • Responsible for verification plan define based on IP design SPEC.
  • Lead verification team to achieve the coverage driven verification goals.
  • Verification Test-Bench maintain and development.
  • Deep understanding on ASIC verification flow, responsible for milestone delivery check

Position Requirements:

  • Master degree with 5+ years or bachelor with 7+ years as an experienced digital IC verification.
  • Experienced in successful tape-out of ASIC chips
  • Familiar to UVM test-bench architecture and experienced on test-bench development.
  • Self-motivation with communication skills (spoken and written English and Mandarin)
  • Be familiar to the coding of SV, Perl/Python, Makefile
  • Experience on leading verification project is ++.

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