Principal Application Engineer - Digital Verification

- Native Vietnamese speaker with good English writing and oral skills

- The candidate should possess CS or EE BS level with  minimum 4- 10+ years, or MS level with  minimum 2- 8+ yrs of industry experience.

 - Minimum 3-8+ years experiences in Digital Logic Design or Verification by EDA solutions.

 - Candidate’s years of experience will be mapped to different grades.

 - Familiar with Digital Simulators (IES, Xcelium, VCS, Questa, etc) with strong simulation debugging skills.

 - Deep hands-on experience on ASIC/SOC verification,  general industry VIP usage or Verification IPs development.

 - Familiar with Verilog/VHDL/SystemVerilog UVM is a must.

 - Knowledge and experiences on emulator/accelerators (Palladium, Zebu, Veloce) is a very big plus.

 - Familiar with SVA and experience on JasperGold is a plus.

 - Knowledge of Linux, shell and Tcl is a must.

 - Scripting skills with Python/Perl is a big plus

 - Familiar of AMBA(AHB, AXI, etc ) and other general interface protocols is a big plus

 - Good program/project management skill

 - Effective team player and good relationship with co-workers, willing to learn

 - Good communication skills in English and a strong desire for working in a global environment with customers and BU people

- Current passport is required with no travel limitations in South East Asia region