Design Engineer, Virtual Solution
Real job — pulled straight from Cadence Design Systems’s careers page · Verified July 4, 2026 · No reposts.
Job description
Cadence Design Systems is hiring a Design Engineer, Virtual Solution — a full-time, based in Shanghai role. Apply directly on Cadence Design Systems's careers page below.
Lead Design Engineer(Virtual Solution)
Location: SHANGHAI
Time Type: Full time
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
- Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
- Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
- Develop end-to-end verification flows including:
- AVIP integration
- Testbench and system modeling
- Bare-metal / driver-level validation
- Optimize solutions for performance, scalability, and emulation efficiency
- Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
- Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
- Support customer enablement, including bring-up, debug, and solution deployment
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience
- Strong expertise in high-speed protocols such as:
- PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
- RTL design experience (SystemVerilog / Verilog)
- C/C++ development experience for modeling, testbench, or system integration
- Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
- Good debugging skills for complex system integration issues
Preferred Qualifications
- Experience developing or using AVIP (Accelerated VIP) solutions
- Experience with end-to-end system validation flows (simulation → emulation → prototyping)
- Knowledge of UVM and verification frameworks
- Knowledge of Qemu/Gem5 or other system emulation projects
- Experience with multi-language environments (SV + C/C++ + Python)
- Familiarity with Emulation/Prototyping flows
- Exposure to AI/ML techniques applied to verification or tooling
- Strong problem-solving skills and ability to work independently
Soft Skills
- Excellent English communication skills (both verbal and written) are required.
- Strong learning capability and adaptability to new technologies
- Ability to collaborate across global teams
- Proactive mindset in problem solving and customer engagement
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Frequently asked questions
What skills are required for Design Engineer, Virtual Solution at Cadence Design Systems?
The required skills for Design Engineer, Virtual Solution at Cadence Design Systems include: PCIe, Ethernet, SystemVerilog, Verilog, C++, C, FPGA, Python, AI, Machine Learning.
What is the seniority level for Design Engineer, Virtual Solution at Cadence Design Systems?
Design Engineer, Virtual Solution at Cadence Design Systems is a Mid Level / Senior level position.
How do I apply for Design Engineer, Virtual Solution at Cadence Design Systems?
You can view the full description and apply for Design Engineer, Virtual Solution at Cadence Design Systems on EchoJobs: https://echojobs.io/job/cadence-design-systems-lead-design-engineer-virtual-solution-4r9sv.