Lead Application Engineer - Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

1. Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, Simulation, Debugger, Formal Verification, VIP products.

2. Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.

3. Train, ramp-up and accompany customer projects.

4. Conduct basic and advanced trainings, presentations and demos as necessary.

5. Providing technical expertise to address clients’ queries, which need expert involvement.

6. Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:

- Minimum 3-5+ years experiences in Digital Logic Design or Verification by EDA solutions.

 - Familiar with Digital Simulators (Xcelium, VCS, Questa, etc) with strong simulation debugging skills.

 - Familiar with Verilog/VHDL/SystemVerilog UVM is a must.

 - Familiar with SVA and experience on JasperGold is a plus.

 - Knowledge of Linux, shell and Tcl is a must.

 - Scripting skills with Python/Perl is a big plus

 - Familiar of AMBA(AHB, AXI, etc ) and other general interface protocols is a big plus

 - Effective team player and good relationship with co-workers, willing to learn

 - Good communication skills in English and a strong desire for working in a global environment with customers and BU people

- Good and fast self-learning ability is a must.

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