Lead Application Engineer

Location: SHANGHAI

Time Type: Full time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

1. Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, Emulation, FPGA prototyping products.

2. Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.

3. Train, ramp-up and accompany customer project.

4. Conduct basic and advanced trainings, presentations and demos as necessary.

5. Providing technical expertise to address clients’ queries, which need expert involvement.

6. Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:

• Requires a BS-EE/CE (MS-EE/CE preferred) with 3-7 years of experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
• Strong knowledge of design debug techniques and a strong understanding in logic design.
• Knowledgeable in verification methodologies for complex EDA environments.
• Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.
• Proficiency in Unix/Linux scripting languages (ksh/bash/csh/perl).
• Experience with emulation, Cadence's Palladium product preferred.
• General knowledge in TBA, Coverage/Assertion flow, Low Power(UPF). UVM experience is a plus.
• Excellent communication skills. Have ability to communicate complex issue to internal teams and customers in a clear and concise manner.

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