Intern in Advanced Node Process Monitor Design

Location: VALBONNE (Sophia)

Time Type: Full time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

We are looking for an intern in Advanced Node Process Monitor Design

Title: Intern

Location: Sophia-Antipolis, France

Duration: 6 months

From: early Q1 2027

Internship Description

Are you curious about advanced technology nodes in microelectronics and eager to gain hands-on experience using them to tackle real engineering challenges? Do you enjoy solving problems and finding smarter ways to work? If so, we'd love to hear from you.

At Cadence, we believe great candidates come from a variety of backgrounds and experiences. You do not need to be an expert in microelectronics or transistor technologies to apply. We are looking for motivated and curious individuals who are eager to learn and excited about exploring how today’s technologies and transistors can be used to address real engineering challenges.

As semiconductor technology scales to ever-shrinking, advanced nodes, transistor variability during production (process variation) presents a critical challenge for integrated circuit design. Because of these variations, two integrated circuits originating from different wafers can exhibit significantly different behaviour.

Efficiently sensing process variations allows systems to be trimmed post-production, enabling an adaptive (rather than purely predictive) design approach, leading to tighter margins and superior performance at the system level. Embedded circuits capable of efficiently tracking process variations have therefore become increasingly critical in modern SoCs.

In this internship, you will work with the Mixed-Signal IP R&D team to investigate available analog and digital circuit options to monitor process variations. After a thorough review of the state of the art, you will design and benchmark these circuits. Positioned at the intersection of circuit design and semiconductor physics, this project offers hands-on design experience in the mixed-signal domain, exposure to cutting-edge technology nodes, and the opportunity to directly contribute to the Cadence Mixed-Signal IP (MSIP) product roadmap.

Internship Requirements

• Currently completing the final year of a master’s degree in electrical and/or electronic engineering.
• A genuine interest in circuit design and semiconductor technology.
• Some exposure to analog design EDA tools, such as Cadence Virtuoso, would be a plus.

How to apply: please upload your resume onto www.cadence.com

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