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Cadence Design Systems

Design Engineering Architect

Bengaluru, India
C C++ SystemVerilog UVM RISC-V ARM AMBA PCIe Perl Python Tcl Formal Verification AI ISA SoC CPU DSP MDV
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Description

Design Engineering Architect

Location: BANGALORE

Time Type: Full time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview:
The DV Architect is a senior technical leadership role responsible for the strategic vision and infrastructure of verification for next-generation Tensilica advanced CPU cores and configurable processors. You will define the methodologies that ensure the functional integrity of highly complex instruction set architectures (ISA).

Key Responsibilities:

  • Methodology Strategy: Define and own the long-term DV architecture, focusing on scalability across multiple processor variants and generations.
  • Verification Infrastructure: Architect simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.
  • Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis.
  • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.
  • Mentorship: Provide technical direction and set the standard for quality and metric-driven verification (MDV) across global teams.

Required Qualifications:

  • B.Tech/M.Tech in ECE with 10+ years of experience in SoC/CPU/DSP verification.
  • Deep expertise in SystemVerilog/UVM and C/C++ for architectural modeling.
  • Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
  • Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
  • Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

Education : BE/BTech/ME/MTech/MS

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Cadence Design Systems
Cadence Design Systems

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