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Design Engineer

Cadence Design Systems

On-site
Cary, NC
Full-time
Entry
3+ yrs
Salary not listedPosted 2w ago

Real job — pulled straight from Cadence Design Systems’s careers page · Verified October 14, 2026 · No reposts.

Job description

Cadence Design Systems is hiring a Design Engineer — a full-time, based in Cary, NC role. Apply directly on Cadence Design Systems's careers page below.

Design Engineer I

Location: CARY

Time Type: Full time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform…

As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.

A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.

Key responsibilities:

  • Define and implement SoC level DFT architecture for large and complex designs.
  • Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
  • Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
  • Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
  • Support post-silicon debug, failure analysis and yield learning.
  • Collaborate with RTL, verification, physical design and operation teams.

Qualifications:

  • BS degree
  • At least 3 years of hands-on experience in SoC DFT.

Must-have skills:

  • Strong expertise in SCAN, ATPG, MBIST.
  • Experience with pre-silicon validation and post-silicon debug.
  • Strong problem solving and debugging skills.
  • Ability to work effectively in a cross-functional engineering environment.

Good-to-have skills:

  • Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
  • Experience with IP-level DFT integration and reuse.
  • Exposure to low-power DFT considerations and complex clocking architectures.
  • Familiarity with manufacturing test flows and silicon yield improvement.

The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Frequently asked questions

What skills are required for Design Engineer at Cadence Design Systems?

The required skills for Design Engineer at Cadence Design Systems include: Perl, Python.

What is the seniority level for Design Engineer at Cadence Design Systems?

Design Engineer at Cadence Design Systems is a Entry level position.

How do I apply for Design Engineer at Cadence Design Systems?

You can view the full description and apply for Design Engineer at Cadence Design Systems on EchoJobs: https://echojobs.io/job/cadence-design-systems-design-engineer-i-gekw8.