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Senior ASIC Design Verification Engineer

Broadcom

On-site
San Jose, CA
Full-time
Senior
10+ yrs
$127k–$226kPosted 3mo ago

Real job — pulled straight from Broadcom’s careers page · Verified May 24, 2026 · No reposts.

Job description

Broadcom is hiring a Senior ASIC Design Verification Engineer — a full-time, based in San Jose, CA role ($127k–$226k). Apply directly on Broadcom's careers page below.

Senior ASIC DV Engineer

Location: USA-CA San Jose Innovation Drive, USA-CA Irvine Alton Parkway Bldg 1

Time Type: Full time

Job Description

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Job Description:

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include:

  • Architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.

  • Using your thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests.

  • Debugging RTL and Gate simulations and work with design engineers to verify fixes.

  • Writing diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.

  • Replicating silicon bugs in simulation environments and validating fixes or SW workarounds.

  • Converting verification tests to test patterns and assisting Test Engineers on ATE vector bring up.

  • Evaluating latest verification methodologies and developing scripts etc. to automate verification flows.

  • Experience understanding and verifying low power silicon for mobile applications with good knowledge of UPF low power verification flow

  • Ability to take customer requirements to verify full chip design and architecture

Qualifications:

  • Bachelors in Engineering and 8+ years of related experience; at this level postgraduate coursework may be desirable or Masters degree in Engineering and 6+ years of related experience

  • MS or PhD is preferred 


Compensation and Benefits


The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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Frequently asked questions

What is the salary for Senior ASIC Design Verification Engineer at Broadcom?

The estimated salary range for Senior ASIC Design Verification Engineer at Broadcom is $127,000 - $226,000 USD per year.

What is the seniority level for Senior ASIC Design Verification Engineer at Broadcom?

Senior ASIC Design Verification Engineer at Broadcom is a Senior level position.

How do I apply for Senior ASIC Design Verification Engineer at Broadcom?

You can view the full description and apply for Senior ASIC Design Verification Engineer at Broadcom on EchoJobs: https://echojobs.io/job/broadcom-senior-asic-dv-engineer-1i03w.