Senior ASIC layout design engineer_BST

Location: Shanghai, Shanghai, cn

Company Description

Do you want beneficial technologies being shaped your ideas? Whether in the areas of mobility solutions, consumer goods, industrial technology or energy and building technology - with us, you will have the chance to improve quality of life all across the globe. Welcome to Bosch.

Job Description

As an ASIC layout designer, you will be responsible for analog layout design from block level, up to top level IC integration and physical verification for advanced ASIC in MEMS sensor. You will work with international design team to ensure the layout delivery on time and in quality, then execute whole tape-out flow together with wafer foundry. Work with digital backend engineer to generate DFE file for P&R and integrated digital layout into whole chip. You will also work with CAD engineers to continuously improve our PDKs and design environment. 

Qualifications

• Bachelor or master degree majored in microelectronics or relevant electrical engineering field (main course: analog circuits, digital circuits, semiconductor device and physics, semiconductor manufacturing). 
• 8 or above years’ experience in analog/mix-signal integrated circuit layout for ADCs, DACs, PLLs, LDOs, Charge pump, bandgap design 
• In-depth knowledge of TSMC28nm ~ 152nm, SMIC110nm, TZ 180nm BCD SOI technologies and design rules
• Able to independently create floorplan on chip level by balance the area, performance, schedule
• Understand the PLS results and give optimize solution to fulfil design spec
• Be able to use at least one programming language to develop scripts to improve the layout effeciency, including C shel, SKILL, TCL, Python
• Be able to evaluate impact of DRC/ERC/ANT/LVS violations to process capability, design performance, and give assessment to project
• Proficiency with Cadence Virtuoso platform as well as Cadence and Mentor Graphics verification and extraction tools, and understand the runset （Calibre, PVS, Assura, etc.… ）
• Understanding of CMOS process side effect and known how to minimize the risk in layout (e.g. 
• lithographic mismatch, LOD effect, WPE effect, latch-up, ESD, antenna, density stress, etc...)
• Be able to analysis EM and IR drop
• Strong problem-solving skills
• Fluent English in writing and speaking.