Staff FPGA Engineer

Location: Taipei, tw

Company Description

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017, and currently has 150+ employees. At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. If you have this type of passion, we invite you to apply for this job.

Job Description

We are seeking a highly skilled FPGA Engineer to focus on the critical communication paths of our security processor. This role is central to ensuring that our hardware interacts seamlessly and securely with the broader server ecosystem (BIOS, BMC, and Host). You will be responsible for implementing OEM-specific logic and performing rigorous end-to-end validation across high-speed serial interfaces.

Key Responsibilities:

• End-to-End Testing: Validate high-speed SPI, eSPI, and LTPI interfaces between the security processor, BIOS, and BMC to ensure absolute signal integrity and strict protocol compliance across all power states.
• OEM Mode Logic: Design, implement, and verify specialized FPGA logic to support OEM mode configurations and secure manufacturing/provisioning flows.
• Project & Tooling Integration: Utilize and extend project-based workflows for hardware description and verification, ensuring that FPGA designs are integrated into the wider system-level CI/CD and simulation environments.
• Vendor & Ecosystem Collaboration: Demonstrate the ability to communicate effectively with IP vendors to resolve complex integration issues and develop customized application layers tailored to Axiado’s unique security architecture.
• Hardware Debugging: Utilize high-speed oscilloscopes, logic analyzers, and internal FPGA debugging tools (e.g., Vivado ILA) to identify and fix physical layer and protocol-level bottlenecks.

Qualifications

• Protocol Expertise: Deep hands-on experience with SPI, eSPI, LTPI, and I2C/I3C protocols, including an understanding of timing requirements and electrical characteristics.
• FPGA Design: Proficiency in Verilog or SystemVerilog for targeting Xilinx, Intel, or Lattice FPGA architectures.
• Application Development: Familiarity with customized application development at the hardware-software interface, allowing for flexible implementation of proprietary features.
• Communication: Strong technical communication skills to act as the primary point of contact for external IP providers and internal firmware teams.
• Education: BS/MS in Electrical Engineering, Computer Engineering, or a related technical field.

Preferred Skills:

• Experience with Open Compute Project (OCP) DC-SCM standards.
• Understanding of Root of Trust (RoT) and secure hardware handoff sequences.
• Familiarity with Project-based workflows or similar modern hardware description methodologies.

Additional Information

Additional Information

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.