Senior ASIC Design Engineer

Team: Control Systems

Location: Boulder, CO, Austin, TX

Commitment: Full-time

Workplace Type: hybrid

At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists, engineers, and business professionals to advance the state-of-the-art in quantum computing.

Atom Computing is seeking a Senior ASIC Designer to design and develop a digital signal processing (DSP) block for our quantum computing systems. You will own the design from requirements definition through silicon bring-up, making key trade-offs across performance, power, area, and system integration constraints.

Reporting to the ASIC Team Lead, you will work closely with cross-functional teams to translate evolving system requirements into production-ready designs. This role requires deep ASIC development expertise, strong systems thinking, and the ability to independently drive complex design work while maintaining alignment with broader system and product goals.

Due to the need for collaboration with Atom’s theory, software, hardware, and optics teams, this role is required to be in the office in Austin, TX or Boulder, CO at least 3 days per week.

Job Responsibilities

Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration.
Work closely with Atom Computing’s quantum physicists, optical engineers, hardware and software engineers to understand use cases and deliver hardware that addresses the needs. 
Participate in the design and development of current FPGA designs. Influence the FPGA design and development process to prepare for ASIC design.

Experience & Education

MS or PhD in Electrical Engineering, or related field.
5+ years of post-degree experience as a hardware engineer. 

Qualifications

Have gone through a complete ASIC design cycle
Experience in digital signal processing algorithms
Proficiency with RTL (SystemVerilog preferred)
Experience in implementing large digital signal processing blocks in RTL
Knowledge of Cadence, Synopsys, or Siemens EDA design tools
Expertise in FPGA, microprocessor, and related digital circuit design and functions