Tech Lead PCB Layout Engineer

Location: Shanghai Shi, China

Department: Advanced Hardware Engineering

At Astera Labs, we seek a motivated and experienced Tech Lead PCB Layout Engineer to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will design complicated PCB layout across multiple fields including high-speed interfaces, power, high-density interconnect, etc. This position will be onsite.

Basic Qualifications

• Strong academic/technical background in electrical engineering or similar degree; Bachelor’s is required;
• 10+ years of experience designing top-tier complex PCB (40,000+ pins, 30+ layer count) across high-speed differential pairs, RF, high-power, high-density interconnect (HDI), etc.
• Capable of full PCB design process from feasibility study, to DFM and Gerber release.
• Have a proven track record with achieving layout design for signal integrity, power integrity, DFT, and DFM.
• Cross-functional design mentality with the electrical design community to develop systems.
• Self-starting, professional, and hands-on work ethic that can execute intense design work in a dynamic environment.
• Proven track record solving problems independently, preferably as a tech lead.
• Prefer previous work experience with oversee customers and proficient in speaking/written English. 

Required Experience

• Proficient in PCB designs with PCIe Gen5/6, Ethernet 112G/224G PAM4, and DDR4/5 applications.
• Proficient in advanced PCB technologies such as micro-vias, blind vias, any layer HDI, back-drilling, and sequential lamination, step gold finger, etc.
• Master EDA tools including Cadence Allegro, Polar SI9000, CAM350 or similar DFM inspection tools, and AutoCAD.
• Proficient in PCB design rules, constraint manager, checklist, etc.
• Possess decent speaking and written English skills.
• Familiar with PCB manufacture and PCB assembly process and capable of handling PCB/PCBA EQ.