Senior Principal Technologist – Memory

Location: San Jose, California, United States

Department: CTO Office

Role Overview

Are you passionate about pushing the boundaries of system, memory, software, and chip architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera’s development of data center memory solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers’ bottlenecks in hyperscale data centers. 

This role is fully in person, in San Jose. Some travel may be required. 

Basic qualifications 

• BS in Electrical or computer engineering, MS or PhD preferred.  
• ≥10 year’s experience developing memory-related solutions and integrating them into systems/racks for data centers 
• Deep experience with PCIe 5/6, and CXL including protocol level depth
• Expertise in OS software integration including memory allocation/management
• Recent experience with silicon architecture and development especially SOCs with memory controllers (DDR*, LPDDR*, HBM, etc)
• Deep expertise and understanding of memory components (DRAM, etc)
• Strong understanding of datacenter system architecture and design challenges
• Strong understanding of “full stack” solutions from silicon to application integration
• Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases
• Ability to dig deeply into technical challenges and use cases
• Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners.
• Demonstrated leadership capabilities with a track record of driving cross-functional technical initiatives and delivering results in a fast-paced environment.
• Willingness to travel occasionally for customer meetings and industry events. 

Preferred experience  

• Expertise in JEDEC-defined memory interface specifications
• Expertise in memory ECC and error handling
• Experience in product integration with BIOS, kernel, OS, tooling, and BMCs
• Experience with board and system design
• Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, JEDEC, CXL, etc.
• Hands-on silicon development experience  

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role is eligible for discretionary bonus, incentives and benefits.