Astera Labs

Senior Emulation Engineer

Santa Clara, CA
R Perl Python
Description

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel. 

We are looking for a Senior Emulation Engineer with hands-on experience on emulation and prototyping for complex ASICs. The ideal candidate would be at ease bringing up an ASIC to do architectural validation, performance testing within the limits of the target platform, driving SW architectural changes. The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces.

Basic qualifications:

  • Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required, and a Master’s is preferred.
  • ≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications.
  • Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision. 
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.

Required experience:

  • Experience in emulation and prototyping technologies like Palladium/Zebu/Veloce or HAPS and FPGA prototyping.
  • Experience in modeling for emulation and prototyping.
  • High level of proficiency in System Verilog and verification environments like UVM.
  • Experience understanding software and hardware co-simulation limitations and debug methods.
  • Experience in programming and scripting languages (like perl/python/C).
  • Currently based locally or open to relocation. 

Preferred experience:

  • Experience with virtualization technologies for emulation like QEMU or Virtual Box
  • Familiarity with Linux codebase and device drivers.
  • Understanding of boot loader technologies like UEFI, ACPI, coreboot.
  • Experience in developing BIOS software to configure and bring up server sub-systems.
  • Working knowledge of PCIe, Ethernet, DDR, SPI, I2C/I3C protocols.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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