Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader of products that are flexible, interoperable, and reliable. We are headquartered in the heart of California’s Silicon Valley, with R&D centers and offices in Taiwan, China, Vancouver and Toronto, Canada, and Haifa, Israel.
We are looking for Senior Design Verification Engineers with proven experience in working on industry standard protocols such as PCIe/CXL/DDR/Ethernet. Using your coding and protocol expertise, you will contribute to the functional verification of the designs from coming up with block level and system level verification plan to writing test sequences, test execution, collecting and closing coverage. You will work with cross functional teams to come up with emulation plan to validate system level test cases.
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required and Masters degree preferred.
- ≥5 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision.
- Knowledge of industry-standard simulators, revision control systems, and regression systems
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
- Experience with interpreting PCIe/CXL standard protocol specifications to come up with verification plan and execute them in simulation and emulation environments.
- Must be able to work independently to develop test-plans, and related test-sequences in UVM to generate stimuli and work collaboratively with RTL designers to debug failures.
- Develop user-controlled random constraints in transaction-based verification methodology. Experience writing assertions, cover properties and analyzing coverage data.
- Must have prior experience using Verification IPs from 3rd party vendors for PCIe/CXL (with focus on Gen3 or above).
- Develop VIP abstraction layers for sequences to simplify and scale verification deployments.
- Currently based locally or open to relocation.
- Physical Layer, Link Layer and Transaction Layer verification expertise in PCIe /CXL protocol.
- Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports.
- Experience in analyzing performance metrics of CXL/PCIe.
- Experience in system level verification for PCIe/CXL.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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