Senior Analog Mixed-Signal IC Layout Engineer

Location: Singapore, Singapore

Department: Analog Layout & Design (SGP_Analog Layout)

We are looking for a Analog / Mixed-Signal Layout Engineer to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools.

Basic qualifications:

• Pursuing BS or MS in EE/CS or related fields.
• Hardware engineering background with an emphasis in VLSI or Computer Architecture.
• Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture.

Required experience:

• Hands-on and knowledge of RTL design languages and tools including Verilog, System Verilog.
• Familiarity with verification methodologies like UVM, functional coverage, assertions.
• Familiarity with any of the scripting languages Python, Perl etc and hands-on experience in C/C++.

Preferred experience:

• Real-world design and/or verification in Verilog/System Verilog.
• Knowledge of high-speed interfaces like PCIe, DDR, HBM, Serdes.
• Familiarity with Synopsys EDA tools.