Principal Silicon Validation Engineer, SerDes/PAM4

Location: San Jose, California, United States

Department: Hardware Engineering

Overview

The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers’ requirements in the highest regard and is solely responsible for certifying a product’s parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.
• 10 + years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
• Proven track record solving problems independently, executing validation plans for complex SoC designs. 

Required Experience:

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet.
• Familiarity with Electrical Compliance section of PCIe Base Spec and CEM Spec
• Working knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQ, CDR, etc and concepts such as PAM4
• Experience in PRBS testing and optimization of high-speed PCIe data links over short, med, and long channels
• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration
• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Preferred Experience:

• Familiarity with PCIe/CXL compliance standards and ability to drive electrical compliance testing at industry workshops
• Hands-on experience with signal integrity, especially as it relates to PCIe testing, Channel Loss budgeting, and de-embedding
• Working knowledge of C or C++ for embedded FW, experience using git-based version control such as github
• Familiarity with PCIe standards and both NRZ and PAM-4 signaling
• Working knowledge of common serial data specifications such as I2C, SPI, etc
• Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues

The base salary range is $185,000 USD - $230,000 USD. Your base salary will be determined based on your experience and the pay of employees in similar positions.