Principal FW/SW Engineer

Location: Toronto, Ontario, Canada

Department: Firmware & Software SCE

Principal Engineer – Embedded Firmware & Software 

Location: Toronto or Ottawa, Ontario (Remote) 
Travel: Occasional travel to Astera Labs’ San Jose headquarters, approximately twice per year, for chip bring-up and project coordination 
Employment: Full-time 

Role Overview 

Join Astera Labs’ Signal Connectivity Engineering team as a Principal Engineer shaping the firmware and software that makes advanced connectivity products adaptive, reliable, and production-ready. You will own embedded software across analog connectivity and Ethernet retimer platforms, from low-level hardware abstraction and calibration through link management, diagnostics, validation, and customer deployment. 

This is a high-impact role at the intersection of embedded systems, mixed-signal hardware, and Ethernet physical-layer behavior. You will work across architecture, lab debug, automation, and customer integration while partnering with silicon, analog, systems, validation, and applications teams. Your work will help deliver purpose-built connectivity for rack-scale AI infrastructure as Astera Labs continues to scale. 

Key Responsibilities 

Firmware Architecture & Product Ownership 

• Own the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs. 

• Design firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry. 

• Architect control algorithms, state machines, and tuning flows that manage analog and high-speed interfaces across process, voltage, and temperature variation. 

• Define software quality gates, validation criteria, and release practices from pre-silicon planning through production deployment. 

Ethernet, Lab Debug & System Integration 

• Debug firmware behavior across Ethernet configurations, link states, and failure modes by tracing interactions among Layer 1 PHY, SERDES, FEC/PCS, MAC, retimer, and gearbox components. 

• Investigate register accesses, embedded SDK behavior, link state machines, PHY telemetry, logs, and real-hardware measurements to identify root causes and deliver targeted fixes. 

• Partner with system validation to develop test plans, automate characterization flows, and verify firmware across corner cases and product configurations. 

• Support customer bring-up, field issue triage, and deployment readiness in collaboration with applications, platform, and silicon teams. 

Technical Leadership & Collaboration 

• Set technical direction, lead architecture and tradeoff discussions, and balance performance, code size, maintainability, and time to market. 

• Serve as a technical authority for mixed-signal firmware, analog control behavior, Ethernet physical-layer debug, and hardware/software integration. 

• Lead design reviews, implementation, code reviews, and difficult debug efforts across firmware, analog, silicon, systems, validation, and applications teams. 

• Mentor engineers and help build the team through recruiting, onboarding, and technical development; people management or a senior technical-lead path may be available as the organization grows. 

Basic Qualifications 

• Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field. 

• 8–12 years of experience developing embedded firmware or software for resource-constrained systems, with ownership from architecture through production. 

• Strong embedded C/C++ skills and deep knowledge of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware. 

• Hands-on experience with Ethernet or high-speed connectivity devices, including Layer 1 PHYs, SERDES, retimers, gearboxes, NICs, switches, or related systems. 

• Solid understanding of physical-layer behavior, link state machines, register-level debug, and hardware/software integration. 

• Experience with feedback systems, adaptive algorithms, calibration, or tuning of analog or mixed-signal subsystems. 

• Proficiency with Microsoft-based development environments and Linux command-line tools, including GCC or Clang, Make, Bash, GDB, and Git. 

• Clear written and verbal communication, systematic debugging skills, and the ability to operate effectively in a fast-moving environment with ambiguity. 

Preferred Qualifications 

• Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field. 

• Python experience for test automation, debug tooling, data analysis, or lab workflows; hands-on experience with Jenkins and CI/CD infrastructure. 

• Familiarity with mixed-signal systems and analog signal paths, including ADC/DAC interfaces, sensor readout, transimpedance amplifiers, transmit drivers, CTLE/DFE equalization, CDR/PLL circuits, or thermal control. 

• Experience with retimer or gearbox firmware, SDK/API development, optical modules or pluggable optics, high-speed copper connectivity, Ethernet PHY subsystems, FEC, PMA, or signal-integrity analysis. 

• Experience using oscilloscopes, BERTs, logic analyzers, and other lab equipment; familiarity with FPGA emulation, pre-silicon validation, RTOS, device drivers, coroutines, mentoring, or recruiting. 

Salary range is CAD $184,500 to CAD $205,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.