Principal Field Applications Engineer

Location: Shanghai Shi, China

Department: Field Applications

Job Description

As an Astera Labs Senior FAE, you will establish yourself as trusted technical advisor to the world’s leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs’ portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by gathering customer requirements, defining new products and working with some of the brightest engineers in the industry.

Basic qualifications

• BS in electrical engineering. Master’s degree in engineering is preferred.
• Minimum of 8 years’ experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Strong organization skills and ability to provide clear and condensed notes and actions.
• Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites
• Fluent in Mandarin and English
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

Required experience

• Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Silicon/System bring-up and debug experience in customer systems.
• Experience with lab equipment including protocol analyzers and oscilloscopes.
• A strong background in high-speed board design techniques, and understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers etc.
• Intermediate level of proficiency in Python for automating system validation and link optimization.
• Able to step through embedded firmware at the SerDes (SoC) or MCU level for debugging.

Preferred experience

• Strong working knowledge of a high speed interface at a physical layer level, associated standards, and debug. Most recent experience with 12G NRZ signaling at a minimum, some experience with 25G NRZ/56G PAM4 preferred.
• Development, support, and experience with PCIe ICs.
• Experience in embedded SW debug or development with firmware, drivers, and BIOS using PCIe technology
• Working knowledge of software/firmware build environments, gcc/Make and GitHub.
• Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others etc.
• Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis.