Manager, Digital Design

Location: San Jose, California, United States

Department: Silicon Engineering CCE1

Role Overview

As Senior Manager/Manager, Digital Design, you will lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment, ensuring that complex designs meet demanding performance, quality, and schedule objectives.

This is an opportunity to influence the development of purpose-built connectivity products at a hyper-growth company, establish scalable design practices, and help deliver silicon that advances the next generation of AI systems.

Key Responsibilities

• End-to-End Chip Development
• Lead digital design execution from product requirements and architecture through RTL, verification, tape-out, and production shipment.
• Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
• Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations.
• RTL Quality and Tape-Out Readiness
• Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tape-out.
• Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
• Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
• Team and Cross-Functional Leadership
• Lead, mentor, and develop a team of 6–8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.
• Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.
• Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.

Basic Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
• 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
• Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.
• Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
• Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Preferred Qualifications

• Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
• Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes.
• Building design blocks with large physical floorplan sizes is a plus
• Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs.
• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.

Salary range is $216,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.