Lead Logic Design Engineer, UALink IP/Subsystem
Real job — pulled straight from Astera Labs’s careers page · Verified September 14, 2026 · No reposts.
Job description
Astera Labs is hiring a Lead Logic Design Engineer, UALink IP/Subsystem — a full-time, based in Bengaluru, Karnataka role. Apply directly on Astera Labs's careers page below.
Lead Logic Design for UALink IP/Subsystem Engineer
Location: Bengaluru, Karnataka, India
Department: Design Engineering CCE2
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Lead Logic Design Engineer – UALink IP/Subsystem
Experience
6–10 years
Job Summary
Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.
Key Responsibilities
- Lead UALink IP/subsystem RTL development.
- Translate protocol requirements into detailed microarchitecture.
- Design high-performance control and data-path logic.
- Work on buffering, arbitration, flow control, ordering, and error handling.
- Develop and review SystemVerilog RTL.
- Drive performance, area, power, and latency optimization.
- Collaborate with verification, SoC integration, and physical design teams.
- Debug complex functional and integration issues.
- Review RTL and mentor engineers.
- Support silicon debug and issue resolution.
Required Skills
- Strong RTL and microarchitecture experience.
- Experience with high-speed interconnects.
- Strong understanding of data movement, flow control, arbitration, and buffering.
- Excellent SystemVerilog/Verilog skills.
- Experience with CDC, lint, synthesis, and timing.
- Strong debugging and technical leadership skills.
Preferred
- Direct UALink experience.
- Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
- Experience with AI/accelerator or high-performance compute SoCs.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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Frequently asked questions
What skills are required for Lead Logic Design Engineer, UALink IP/Subsystem at Astera Labs?
The required skills for Lead Logic Design Engineer, UALink IP/Subsystem at Astera Labs include: SystemVerilog, Verilog, PCIe, Ethernet.
What is the seniority level for Lead Logic Design Engineer, UALink IP/Subsystem at Astera Labs?
Lead Logic Design Engineer, UALink IP/Subsystem at Astera Labs is a Senior / Manager level position.
How do I apply for Lead Logic Design Engineer, UALink IP/Subsystem at Astera Labs?
You can view the full description and apply for Lead Logic Design Engineer, UALink IP/Subsystem at Astera Labs on EchoJobs: https://echojobs.io/job/astera-labs-lead-logic-design-for-ualink-ip-subsystem-engineer-7zgy7.