Design Verification Student
Location: Tel Aviv-Yafo, Tel Aviv District, Israel
Department: ASIC Engineering
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Design Verification Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.
As a Design Verification Student, you will be at the forefront of quality, learning how to ensure that the chips powering the world's largest AI clusters are bug-free and robust.
This isn't just about running tests - it’s an opportunity to learn advanced verification methodologies (UVM/SystemVerilog) alongside world-class engineers. You will support the development of sophisticated testbenches and help verify high-performance digital blocks that sit at the heart of AI infrastructure.
Key Responsibilities
- Assist in building and maintaining System Verilog/UVM-based testbenches, including monitors, checkers, and functional coverage models
- Run simulations, analyze failures, and work with the design team to debug and resolve RTL issues
- Help define and implement functional coverage and assertions to ensure all "corner cases" of the design are tested
- Utilize and improve scripting (Python/Tcl) to streamline verification flows and result reporting
- Partner with Design Engineers to understand block specifications and ensure the verification plan matches the design intent
Basic Qualifications
- Pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
- Ability to work at least 2 days a week at our Haifa/Tel Aviv center
- Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
- Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
- A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
- Fluent in Hebrew and English with the ability to work effectively in a team environment
Preferred Qualifications
- Completed courses in VLSI, Digital Systems, or Computer Architecture
- Proficiency in Python, Perl, or Tcl
- Any prior exposure to UVM/OVM or constrained-random verification is a major plus
- Basic understanding of protocols like PCIe, Ethernet, or DDR
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
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